Abstract: Pipeline synchronization device for transferring data between clocked devices having different clock frequencies. The Pipeline synchronization device comprises a mousetrap buffer for exchanging data with one of said external devices said mousetrap buffer having a signalling output for coordinating the data exchange with the external device. The pipeline synchronization device comprises further a synchronizer adapted to synchronizing the change in a signalling output with the clock of the external device.

Abstract: A method for communicating with a processor event facility is provided. The method makes use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.

Abstract: A mixed architecture system on chip is provided by combining a CoreConnect system on chip architecture with an AMBA system on chip architecture. To eliminate data transfer and bus error that could occur in the mixed architecture, an additional peripheral bus and bridge are provided to manage communication with AHB resources.

Abstract: An apparatus comprises a plurality of logically independent processors, a system bus, and a cache control and bus bridge device in communication with the plurality of processors such that the cache control and bus bridge device is logically interposed between the processors and the system bus, and wherein the processors and cache control and bus bridge device are disposed in a module form factor such that the apparatus is a drop-in replacement for a standard single processor module.

Abstract: A method for bridging between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a method for bridging between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI).

Abstract: The present invention provides an optical DVI cable and optical signal transmission equipment which can prevent the leakage of laser light to the outside. The optical DVI cable includes (1) a transmission side unit having a laser light emitting element unit, and configured and arranged to convert input electrical signals into optical signals and to transmits the optical signals, (2) a reception side interface unit configured and arranged to receive the optical signals transmitted from the transmission side interface unit, and (3) a connecting cable having metal wires to supply power to the laser light emitting element unit, and optical fibers to transmit optical signals. The transmission side unit may include a power supply terminal. In this case, the metal wires supply power to the laser light emitting element unit from the transmission side unit via the reception side unit.

Abstract: It becomes possible for a user to set a transmission or reception channel arbitrarily and easily. Each of equipment connected to an IEEE 1394 bus may include a register provided within a RAM 113 to thereby set a transmission or reception default channel. If channels used in the transmission and the reception are not set when the transmission is started, then default channel may be used. When equipment is set to a channel setting mode by operating an operation section 116, a control section 112 may display a channel setting picture on a display section 115. In this state, a user may select a set channel by operating an up-key 116a and a down-key 116b of the operation section 116. Thereafter, when a user operates a “YES” key 116c, the control section 112 may write a selected channel in the above-mentioned register, and ends a default channel setting operation. A user can set the transmission or reception channel arbitrarily and easily.

Abstract: A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.

Abstract: A laptop computer and mating docking station where the docking station provides power to the laptop computer over power rails of the Universal Serial Bus (USB) interface. The laptop computer has laptop docking logic that both provides power in accordance with standard USB protocol, and also receiving power across the power rails of the USB interface. Likewise, the docking station has a docking station dock logic that establishes communication with the laptop docking logic across the USB power rails. Once positive communication is established, the dock station provides voltages on the USB power rails sufficient to power the laptop computer as well as charge the laptop's battery.

Abstract: A peripheral for notifying a USB-connected upper apparatus of a device descriptor and allowing the upper apparatus to specify a communication partner destination by the function information shown in the device descriptor has: a peripheral function information holding unit which holds function information showing functions of the peripheral; a dependent peripheral function information holding unit which holds function information showing functions of a USB-connected dependent peripheral; and a USB control unit which reads out one of the function information held in those holding units by a selecting instruction and notifies the upper apparatus of the device descriptor in which the read-out function information is shown. A peripheral which can realize a multi-function without developing a dedicated driver and installing it into a PC is provided.

Abstract: A system and method for supporting multiple graphics processing units (GPUs) includes a first communication path coupled to a root complex device and a first connection point of a first GPU. A second communication path is coupled to the root complex device and a first set of switches. The first set of switches is configured to route communications between the root complex device to either a second connection point of the first GPU via a second set of switches or to a first connection point of a second GPU. The second set of switches is coupled to a second connection point of the first GPU. The second set of switches is configured to route communications to and from the second connection point of the first GPU and to either the root complex device via the first set of switches or to a second connection point of the second GPU.

Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

Abstract: A system and method for transferring information in a multi-channel, point-to-point environment are described. In one embodiment, a number of processing chips are connected to a bridge bus. A bridge is connected to the bridge bus and to a system bus. In addition, a memory is connected to the bridge.

Abstract: Multiple memory channels of a multi-channel memory architecture are effectively bridged together to enable data traffic associated with various nodes in daisy chain arrangement to be communicated over both memory channels. For example, a daisy chain arrangement of nodes, such as FB-DIMM memory modules disposed in a first memory channel may be coupled to a second memory channel, with support for communicating data associated with one of the nodes over either or both of the first and second memory channels.

Abstract: A communication control circuit that performs the process of receiving a response to send data in synchronous transfer mode within a certain period of time without using an external control circuit. A permissible time calculation section calculates permissible time for receiving response data corresponding to send data sent to each of communication nodes connected to a serial bus from data length of the send data, data length of the response data, and a number of the communication nodes to which the send data is sent on the basis of communication cycles specified in the synchronous transfer mode. A response time management section determines whether the response data received as a response to the send data sent via the serial bus is received within the permissible time calculated by the permissible time calculation section. As a result, time taken to receive the response data corresponding to the send data is guaranteed.

Abstract: A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. According to one embodiment, a node associated with a contended lock is monitored; and a processor seeking the contended lock is put to sleep until a monitor event occurs.

Abstract: A system and method for guaranteeing transactional fairness among multiple requesters contending for a common resource in a cache-coherent multiprocessor system is described. Batch processing is used to control servicing of multiple requests made by multiple requesters (such as processors) of a common resource in a cache-coherent multiprocessor system. Specifically, identification numbers are assigned to requests as they are received from the multiple requesters. The identification numbers are then used in conjunction with batch processing to prioritize and guarantee servicing of the requests.

Abstract: In a system having an arrangement that a CPU (101) connected to a bus (107) via bus bridge (103) and a CPU 102 connected to a bus (107) via bus bridge (104), when the bus bridge (103) receives a semaphore acquisition request from the CPU (101), it controls acquisition of a semaphore on the basis of a semi_out signal received from the bus bridge (104) and a priority order received via a signal line (112).

Abstract: Techniques are described herein for handling lock-related inconsistencies. As mentioned above, such inconsistencies occur when two or more sets of lock information, relating to the same resource, convey inconsistent information about locks requested and/or granted on that resource. In general, the techniques involve causing the locally-stored lock information about a resource to be sent to the master node of the resource. The master node of the resource compares the lock information thus received against the lock information maintained by the master node. Based on the comparison, the master node determines how to resolve the lock-related inconsistency, and sends messages to those nodes that need to change their local lock information for the resource. Once all of the lock information has been made consistent, the resource made available for access.

Abstract: Round robin arbitration system includes a first round robin arbitration module and a second round robin arbitration module. The first round robin arbitration module has a first bit width. It is configured to partition a plurality of requests into a plurality of blocks of requests, to select a block having one or more active requests using round robin arbitration, and to generate a first index corresponding to the selected block. The second round robin arbitration module has a second bit width. It is configured to store each request of the selected block, to select each active request of the selected block using round robin arbitration, to generate a second index corresponding to the selected active request, and to generate a first signal for synchronizing operation of the first and second modules. The round robin arbitration system has a bit width that is a product of the first and second bit width.