Abstract: A programmable logic device with an embedded operating system is disclosed. The programmable logic device includes a bus, memory, a number of bidirectional communication ports, a switching mechanism. The operating system embedded in the programmable logic device responds to input received through the ports by either sending data to a device connected to one such port, or by instructing the switching mechanism to establish a direct connection between two such ports. This device may be included as part of a larger computer system.

Abstract: A Universal Serial Bus (USB) device uses a same elasticity buffer for buffering packets for multiple different ports and only necessary packet detection circuitry is associated with the individual ports. A collision detection circuit is further included corresponding with information received from the packet detection circuitry. This simplified universal elasticity buffer architecture reduces the complexity and cost of the USB device.

Abstract: An embodiment includes a communication medium coupled to a plurality of the functional blocks in an integrated circuit. Three or more of the initiator functional blocks communicate with a target functional block by sending requests having an associated identifier to indicate a transaction stream that the request is part of. At least a first and a second of buffer are associated with the target functional block at an interface of the target functional block to the communication medium and receive requests having the associated identifiers from the three or more initiator functional blocks through a shared common connection point for the interface. The communication medium implements a mapping algorithm to map requests from a first initiator functional block as well as requests from a third initiator functional block to a first dedicated buffer based on the associated identifiers.

Abstract: A processor including an integrated system interface unit configured to manage multiple I/O interfaces and multiple protocols. A processor includes a plurality of processing cores, a cache comprising a plurality of banks, and a system interface unit coupled to the processing cores and the cache. The system interface unit includes an inbound unit configured to receive inbound transactions from a first I/O unit and a second I/O unit, and an outbound unit configured to convey outbound transactions to either the first I/O unit or the second I/O unit. Each of the first and second I/O units is configured to support different protocols. Prior to conveying transaction data to the system interface, the first I/O unit and second I/O units reformat transaction data to conform to a common format. The system interface receives and stores transaction data in either queues dedicated for cacheable transactions or queues dedicated for non-cacheable transactions.

Abstract: A method for connecting an externally accessible shared serial port to one of a plurality of target serial ports is provided. The target serial ports are associated with a plurality of different application cards within a shelf assembly. The method includes receiving, from an external device connected to an externally accessible shared serial port, a request for a connection between the externally accessible shared serial port and one of a plurality of target serial ports within a shelf assembly associated with a plurality of different application cards, and determining whether shelf resources are available to connect the externally accessible shared serial port to the requested target serial port. In response to determining that shelf resources are available, the externally accessible shared serial port is connected to the requested target serial port.

Abstract: An even-driven interrupt processing is efficiently carried out in a multiprocessor system. A main control unit 112 executes a main process as a processing for controlling an apparatus in a unified manner. A sub-control unit 116 executes a task assigned by the main control unit 112 during the execution of the main process, as a sub-process. An event detector 162 detects an event occurrence upon which an interrupt task is to be preferentially executed during the execution of the main process. An interrupt notification unit 164 notifies the sub-control unit 116 of interrupt information indicative of an interrupt task in response to the detected event. The sub-control unit 116 notified of the interrupt information executes the interrupt task specified by the interrupt information, as a sub-process.

Abstract: A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. In one embodiment, a memory to store instructions to perform functions of a monitoring mechanism is provided. The monitoring mechanism having a first logic to cause a processor to exit a sleep state in response to an event, wherein exiting the sleep state comprises resuming control of processing resources that were relinquished by the processor during the sleep state. The monitoring mechanism having a second logic to disable monitoring of a node associated with a contended lock after the processor exits the sleep state.

Abstract: A mechanism for priority control in resource allocation for low request rate, latency-sensitive units is provided. With this mechanism, when a unit makes a request to a token manager, the unit identifies the priority of its request as well as the resource which it desires to access and the unit's resource access group (RAG). This information is used to set a value of a storage device associated with the resource, priority, and RAG identified in the request. When the token manager generates and grants a token to the RAG, the token is in turn granted to a unit within the RAG based on a priority of the pending requests identified in the storage devices associated with the resource and RAG. Priority pointers are utilized to provide a round-robin fairness scheme between high and low priority requests within the RAG for the resource.

Abstract: A USB device may be simultaneously configured and accessed by two or more USB hosts. The USB device may include separate upstream ports and buffers for each host, and a multi-host capable device controller configured to respond to simultaneous USB requests received from more than one host. The USB device may maintain a dedicated address, configuration, and response information for each host. The USB device may include a shared USB function block, and a multi-host controller configured to establish concurrent respective USB connections between the shared USB function block and two or more USB hosts, to allow the two or more USB hosts to simultaneously configure the USB device for the shared USB function. The multi-host controller may be configured to receive and respond to simultaneous respective USB access requests for the shared USB function sent by the two or more USB hosts.

Abstract: A storage controller receives an interrupt control directive from a host. The storage controller generates a first plurality of interrupts, in response to access requests received from the host for at least one storage device coupled to the storage controller, wherein the first plurality of interrupts indicates whether access to the at least one storage device is allowed to the host. The storage controller generates a second plurality of interrupts, wherein the second plurality of interrupts comprises unsolicited interrupts for the host that are different from the first plurality of interrupts. The storage controller controls how many of the first plurality of interrupts and how many of the second plurality interrupts to send to the host, based on the received interrupt control directive.

Abstract: An interconnect apparatus, for example a switch, supports PCI-Express. The apparatus has a first plurality of ports configurable as upstream ports, each connectable to a respective host, and at least one port configurable as a downstream port connectable to a device. The apparatus is operable to support sharing of the device resources between hosts.

Abstract: A storage controller receives an interrupt control directive from a host. The storage controller generates a first plurality of interrupts, in response to access requests received from the host for at least one storage device coupled to the storage controller, wherein the first plurality of interrupts indicates whether access to the at least one storage device is allowed to the host. The storage controller generates a second plurality of interrupts, wherein the second plurality of interrupts comprises unsolicited interrupts for the host that are different from the first plurality of interrupts. The storage controller controls how many of the first plurality of interrupts and how many of the second plurality interrupts to send to the host, based on the received interrupt control directive.

Abstract: A bus request control circuit provided in a signal processing circuit having a higher priority in an arbitration circuit includes a request signal transmitting section which transmits a request signal to request a bus right to the arbitration circuit. A request acknowledge signal receiving section receives a request acknowledge signal transmitted from the arbitration circuit in response to the request signal transmitted to the arbitration circuit. Further, the request signal from the request signal transmitting section is transmitted after lapse of a predetermined time since reception of the request acknowledge signal.

Abstract: A data aggregation-distribution apparatus includes a plurality of port route units and a data processing unit. Every port route unit has a sending buffer and a receiving buffer. The data processing unit has a data aggregation unit and a data distribution unit. The data aggregation unit and the data distribution unit are used to increase the bandwidth of a communication system.

Abstract: Once accepting an interrupt, the control is such as to not accept any interrupt including that highest priority within the group to which the interrupt about to be processed belongs by referring to the interrupt management table. Then the vector number for the highest priority in the group from among the received interrupts is selected. Then the processing of a handler for the selected vector number is executed. The priority of the executed interrupt processing is reset to the lowest priority in the group.

Abstract: A data bus interface for a control unit, in particular for a motor vehicle control unit is described, as well as a control unit, in particular a motor vehicle control unit, having a data bus interface for accessing a data bus for communicating with another control unit via the data bus. A data bus interface may be used with a particularly high degree of flexibility and be manufactured economically. The data bus interface includes two arithmetic units, in particular two microprocessors, which communicate with each other via an internal data bus; and two transceivers which are connected either to the same external data bus or to two different external data buses and are interconnected with the two arithmetic units in such a way that the two arithmetic units are connected either to the same external data bus or to the two different data buses.

Abstract: A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.

Abstract: A signal protocol assembly is adapted to bridge electronic communications across a plurality of communications platforms allowing a plurality of electronic devices to transfer data therebetween. The signal protocol assembly is electrically connected between the electronic communications device and a communications hub to help facilitate in the translation of communications from the electronic communications device to a third party independent communications protocol, and back when necessary. The signal protocol assembly includes a microprocessor for receiving data from each of the plurality of electronic devices. The signal protocol assembly also includes a plurality of ports electrically connected to the microprocessor for selectively connecting a portion of the plurality of electronic devices in electrical communication with the microprocessor.

Abstract: A method of Universal Serial Bus (USB) data transfer is provided. In one embodiment, a USB device supports a bulk-only transmission mode to transfer data with a USB host, and the USB device comprises a bulk endpoint buffer storing data transferred between the USB device and the USB host through a bulk endpoint of the USB device and an interrupt endpoint buffer storing data transferred between the USB device and the USB host through an interrupt endpoint of the USB device. A first portion of data stipulated to be transferred through the bulk endpoint is stored with the interrupt endpoint buffer. A data path through which data is transferred between the USB host and the USB device is switched to lead to either the bulk endpoint buffer or the interrupt endpoint buffer with a multiplexer.

Abstract: A shared USB device may be simultaneously configured and accessed by two or more USB hosts by using a multi-host capable device controller. The multi-host capable device may include separate upstream ports and buffers for each host, and may be configured with the capability to respond to USB requests from more than one host. The multi-host capable device may maintain a dedicated address, configuration, and response information for each host. Each host may therefore establish a dedicated USB connection with the sharing device without the sharing device having to be re-configured or re-enumerated each and every time the upstream hosts alternate accessing the USB device.