Patents Examined by Jermele M. Hollington
  • Patent number: 11327098
    Abstract: During frequency detection, a constant current source outputs an output current to charge a variable capacitor for multi-period. In a calibration mode, according to a comparison result between a cross voltage of the variable capacitor and a reference voltage, a capacitance value of the variable capacitor is adjusted. In a monitor mode, according to a reference frequency and the cross voltage of the variable capacitor, a frequency under test of a circuit under test is detected.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: May 10, 2022
    Assignee: GRACE CONNECTION MICROELECTRONICS LIMITED
    Inventors: Pei Wei Chen, Fang-Ren Liao
  • Patent number: 11329471
    Abstract: An arc detection circuit includes a current detector and arc determination unit. The current detector detects a current flowing through a transmission line which connects an electric power supply device and an electric power conversion circuit. The arc determination unit calculates, from a result of measurement of the current, an area of interest and an area for comparison. The area of interest is an area of a region of interest defined by a predetermined frequency range and predetermined time for determination. The area for comparison is an area of a portion in which detected strength exceeds a predetermined strength threshold in the region of interest. The arc determination unit determines an electric arc has occurred when a ratio between the area of interest and the area for comparison exceeds a predetermined area-ratio threshold.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: May 10, 2022
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Tatsuo Koga, Atsushi Okita, Mitsuru Kaji
  • Patent number: 11328636
    Abstract: The present invention provides a clamper and a lighting fixture. An elastic layer for contacting a panel is disposed on a rotatable clamping portion. In addition to that, a distance from a lowest point of one end of the panel clamped by the rotatable clamping portion to a carrier plate supporting a polarizer at one side of the panel adjacent to a thin film transistor is greater than a thickness of the polarizer. Accordingly, the present invention prevents the panel and the polarizer at one side of the panel adjacent to the thin film transistor from being damaged from clamping.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: May 10, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Junfeng Zheng
  • Patent number: 11327111
    Abstract: A chip testing system and an environment control apparatus are provided. The chip testing system includes the environment control apparatus, a central control device, and a chip testing device. The environment control apparatus includes an apparatus body and a pressing device. When the chip testing device is disposed in an accommodating chamber of the apparatus body, and the central control device controls the pressing device to press a plurality of side surfaces of a plurality of chips carried by the chip testing device, the central control device controls the chip testing device to perform a testing operation to the chips. After the chip testing device performs the testing operation to the chips, a plurality of movable members of the pressing device protrude from a contacting surface of the pressing device and push the chips to separate the chips and the contacting surface.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: May 10, 2022
    Inventors: Chen-Lung Tsai, Gene Rosenthal
  • Patent number: 11320486
    Abstract: An optical device is formed on an optical IC chip. The shape of the optical IC chip is rectangular or parallelogram. The optical device induces: an optical device circuit; a first optical waveguide that is coupled to the optical device circuit; a pad that is electrically connected to the optical device circuit; a grating coupler; and a second optical waveguide that is coupled to the grating coupler. The pad is formed in a region close to a first side of the optical IC chip. The grating coupler is formed in a specified region, which is not close to the first side, on the optical IC chip. The first optical waveguide and the second optical waveguide are respectively extended to an edge of the optical IC chip.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: May 3, 2022
    Assignee: FUJITSU OPTICAL COMPONENTS LIMITED
    Inventor: Masaki Sugiyama
  • Patent number: 11320476
    Abstract: An eddy current system and methods of performing operations on a structure using the eddy current system are presented. The eddy current system comprises an ion beam source and a magnetic field source with at least one of variable output intensity or variable output orientation.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: May 3, 2022
    Assignee: The Boeing Company
    Inventor: Brian Jay Tillotson
  • Patent number: 11320252
    Abstract: A method of installing a stroke sensor that enables the stroke sensor to be adjusted in a simple process is provided. The method has the steps of: arranging a second magnet, relative to the magnetic field detecting element, at a physically determinable first reference position and obtaining an indicator value S1; attaching the first magnet and the magnetic field detecting element to structures different from each other, respectively, and positioning the first magnet, relative to the magnetic field detecting element, at a physically determinable second reference position, and obtaining an indicator value S2, wherein the second reference position corresponds to the first reference position; calculating ?S=S1?S2, wherein ?S is a difference between the indicator value S1 and the indicator value S2; and modifying a process in the processor such that a sum of the indicator value S and ?S is outputted.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: May 3, 2022
    Assignee: TDK Corporation
    Inventors: Takahiro Moriya, Toshio Ishikawara, Toshihiko Oyama
  • Patent number: 11320479
    Abstract: An electronic device includes: a detection circuit configured to determine one or more operating data, one or more device sensor data, or a combination thereof associated with operation of the electronic device; a trigger circuit operably coupled to the circuit, the trigger circuit configured to generate a stress input based on detecting one or more target criteria from the one or more operating data, the one or more device sensor data, or a combination thereof; and a degradation sensor operably coupled to the trigger circuit, the degradation sensor having a threshold voltage and being configured to record the target criteria that occurs during operation of the electronic device, wherein the degradation sensor is configured to record the target criteria based on degradation of the threshold voltage according to the stress input.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: May 3, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Todd J. Plum, Scott D. Van De Graaff
  • Patent number: 11313702
    Abstract: A system and method for monitoring analog front-end (AFE) circuitry of an inductive position sensor. A redundant AFE channel is provided and alternatively utilized with a sine AFE channel or a cosine AFE channel of the AFE circuitry to obtain a voltage difference that may result in a detection angle error at the electronic control unit (ECU) of the inductive position sensor.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: April 26, 2022
    Assignee: Microchip Technology Inc.
    Inventors: Stephane Le Goff, Mathieu Sureau, Jebas Paul Daniel T, Naveen Cannankurichi, Subhasis Sasmal, Sunny Joel
  • Patent number: 11313936
    Abstract: Probe systems and methods of characterizing optical coupling between an optical probe of a probe system and a calibration structure. The probe systems include a probe assembly that includes an optical probe, a support surface configured to support a substrate, and a signal generation and analysis assembly configured to generate an optical signal and to provide the optical signal to the optical device via the optical probe. The probe systems also include an electrically actuated positioning assembly, a calibration structure configured to receive the optical signal, and an optical detector configured to detect a signal intensity of the optical signal. The probe systems further include a controller programmed to control the probe system to generate a representation of signal intensity as a function of the relative orientation between the optical probe and the calibration structure. The methods include methods of operating the probe systems.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: April 26, 2022
    Assignee: FormFactor, Inc.
    Inventors: Joseph George Frankel, Kazuki Negishi
  • Patent number: 11313891
    Abstract: A display device including a first substrate including a display area and a non-display area, a circuit film connected to the first substrate, a printed circuit board (PCB) connected to the circuit film, and a first inspection pad, a second inspection pad, and a third inspection pad located in the non-display area and a bridge configured to electrically connect the first inspection pad, the second inspection pad, and the third inspection pad. The circuit film includes a first line electrically connected to the first inspection pad, a second line electrically connected to the second inspection pad, a third line electrically connected to the third inspection pad, and a branch point configured to branch at least one line from the first line, the second line, and the third line into two sub-lines. The PCB includes a test pad unit connected to the first line, the second line, and the third line.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: April 26, 2022
    Inventors: Chung Seok Lee, Eun Byul Kim, Kyeong Yeol Heo
  • Patent number: 11313904
    Abstract: A testing device includes a transmitter circuit, a receiver circuit, and a loopback circuit. The transmitter circuit is configured to receive a plurality of first test signals. The receiver circuit is configured to receive input data from a plurality of pads in a normal mode. The loopback circuit is coupled to the plurality of pads and input terminals of a sampler circuit, and the loopback circuit is configured to transmit the plurality of first test signals from the transmitter circuit to the input terminals of the sampler circuit, in order to generate test data for subsequent analysis.
    Type: Grant
    Filed: November 24, 2019
    Date of Patent: April 26, 2022
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Chung Chen, Tsai-Ming Yang, Po-Shing Yu
  • Patent number: 11313661
    Abstract: An electromagnetic induction type coordinate positioning apparatus includes a first induction coil, a second induction coil, a first amplification circuit, a second amplification circuit, and a control circuit. The first induction coil and the second induction coil respectively generate a first induction signal and a second induction signal when a pointer device comes close. The first amplification circuit and the second amplification circuit may be electrically connected to the first induction coil and the second induction coil, to receive the first induction signal and the second induction signal. The control circuit controls the first amplification circuit and the second amplification circuit to amplify the first induction signal and the second induction signal, so that a power level of the amplified first induction signal and a power level of the amplified second induction signal reach a first predefined level and a second predefined level.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: April 26, 2022
    Assignee: Shenzhen Pu Ying Innovation Technology Corp., LTD.
    Inventor: Chung-Wen Hsu
  • Patent number: 11307240
    Abstract: The present disclosure provides an analysis method for a semiconductor device for analyzing a plurality of process parameters for manufacturing a HKMG fin field effect transistor. The analysis method specifically includes: establishing a plurality of process parameter models by grouping the plurality of process parameters in pairs; performing sensitivity analysis on each of the process parameter models; extracting a plurality of key process parameter models from the plurality of process parameter models based on the results of the sensitivity analysis; and performing data mining on the plurality of key process parameter models to determine a plurality of key process parameters and their correlations among the plurality of key process parameters. According to the analysis method provided by the present disclosure, related process parameters are highlighted by data mining and grouping, and the source of process parameter changes is explained. It is possible to adjust the process.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: April 19, 2022
    Assignee: Shanghai Huali Integrated Circuit Mfg. Co. Ltd.
    Inventor: Ping-Hsun Su
  • Patent number: 11307017
    Abstract: In one aspect, an angle sensor includes analog circuitry configured to generate an analog value having a tangent value, an analog-to-digital converter configured to convert the analog value to a digital value and digital circuitry configured to receive the digital value. The analog circuitry includes a plurality of magnetoresistance elements that include a first magnetoresistance element configured to provide a cosine value indicative of a magnetic field along a first axis and a second magnetoresistance element configured to provide a sine value indicative of the magnetic field along a second axis orthogonal to the first axis. The tangent value is determined by the cosine and sine values. The digital circuitry includes an angle processor configured to use the digital value and a fixed value in an arctangent algorithm to generate an angle of a direction of the magnetic field.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: April 19, 2022
    Assignee: Allegro MicroSystems, LLC
    Inventor: HernĂ¡n D. Romero
  • Patent number: 11307250
    Abstract: A Scanning Time-Resolved Emission (S-TRE) microscope or system includes an optical system configured to collect light from emissions of light generated by a device under test (DUT). A scanning system is configured to permit the emissions of light to be collected from positions across the DUT in accordance with a scan pattern. A timing photodetector is configured to detect a single photon or photons of the emissions of light from the particular positions across the DUT such that the emissions of light are correlated to the positions to create a time-dependent map of the emissions of light across the DUT. The scanning system is configured to update the time-dependent map of the emissions based on combinations of the emissions of light at certain locations.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: April 19, 2022
    Assignee: International Business Machines Corporation
    Inventors: Franco Stellari, Peilin Song
  • Patent number: 11306913
    Abstract: The present invention is a storage tank including: a tank; a tank main body that stores a liquid material; a cover body that covers an opening of the tank main body; a support body that is positioned opposite to the cover body; a seal body that is sandwiched by a flange provided at the opening end of the tank main body and the cover body; and tightening members that tighten the cover body and the support body, and is capable of, even when the thickness of the flange provided at the opening end of the tank main body is thin, attaching the cover body on the flange while maintaining a contact property.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: April 19, 2022
    Assignee: HORIBA STEC, Co., Ltd.
    Inventor: Shinji Taniguchi
  • Patent number: 11300592
    Abstract: A terminal block for current measurement in a power grid. The terminal block includes a shunt and a temperature sensor, and is configured to be connected to an Intelligent Electronic Device IED and a primary device. Furthermore, a respective IED and a system for current measurement including the IED and the terminal block are disclosed as well as a method for calibration of the system and a method for current measurement in power grids. A voltage measurement unit in the IED is adapted to measure a voltage drop at the shunt; a current flowing through the shunt can be calculated from the temperature and from calibration data. The terminal block enables a particularly efficient calibration method.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: April 12, 2022
    Assignee: Hitachi Energy Switzerland AG
    Inventors: Calogero Bona, Francesco Rizzo, Jimmy Kjellsson
  • Patent number: 11300611
    Abstract: An image test system includes a test assembly and an image capture card. The test assembly is provided for capturing test signals from test objects, and incudes a first transmission interface, a second transmission interface, and an interface conversion circuit. The interface conversion circuit is connected with the first transmission interface, and converts signal transmission forms of the test signals. The second transmission interface is connected with the interface conversion circuit. Besides, the image capture card is provided for connecting with the second transmission interface, and captures image data from the test signals.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: April 12, 2022
    Assignee: KING YUAN ELECTRONICS CO, LTD.
    Inventors: Pin-Yan Tsai, Po-Kuan Sung, Kuang-Che Cheng, Hung-Chan Lin
  • Patent number: 11302491
    Abstract: A high speed arc suppressor and method include a first phase-specific arc suppressor configured to suppress arcing across contacts of the power contactor in a positive domain and a second phase-specific arc suppressor configured to suppress arcing across the contacts in a negative domain. First and second high speed switches are configured to enable and disable operation of an associated one of the first and second phase-specific arc suppressors. First and second drivers are configured to drive the first and second high speed switches.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: April 12, 2022
    Assignee: Arc Suppression Technologies
    Inventors: Reinhold Henke, Warren Kahle