Abstract: First and second electrical components on an integrated circuit chip are electrically connected respectively to a wire bonding pad and to a probe contacting area of a size significantly less than the bonding pad. The pad and contacting area are electrically isolated whereby both components can be separately electrically tested by test probes contacting each of the pad and the contact area. After the components have been tested, the bonding pad and the probe contact area are electrically connected together for electrically connecting the first and second components. The electrical connection is made by bonding a terminal wire to the bonding pad as well as to an extension from the contact area substantially filling a space within the bonding pad and underlying the joint formed between the terminal wire and the bonding pad.

Abstract: An integrated circuit package. The package includes a substrate which has a first surface, a second opposite surface and four corners. Each corner has a conductive plane and at least one via. The vias connect the conductive planes of the first surface with corresponding conductive planes located on the second surface of the substrate. An integrated circuit is mounted to the first surface of the substrate and enclosed by plastic. Solder balls are attached to the conductive planes and a number of individual solder pads located on the second surface of the package. The contacts are connected to a printed circuit board. A lid is attached to the conductive planes at the four corners of the substrate. Some of the heat generated by the integrated circuit conducts through the substrate and into the printed circuit board. Some of the heat within the substrate conducts into the lid through the conductive planes located at the corners of the package.

Abstract: A semiconductor sensor chip such as an acceleration sensor chip and other electronic components such as controlling semiconductor chips are mounted on and connected to conductor patterns formed on a ceramic package. The ceramic package is heated together with a cap to hermetically seal the ceramic package containing the sensor chip and electronic components therein. The conductor pattern formed on the ceramic package is composed of a base film of, i.e., tungsten, an intermediate film of nickel plated on the base film and a thin surface film of gold which is formed on the intermediate film by flash plating. The conductor patterns are also formed at outside portions of the ceramic package. The ceramic package is mounted on a printed board by soldering at portions where the conductor patterns are formed. Though the surface gold film is thin and made at a low cost, it provides an excellent surface of the conductor patterns for securing a good solder wettability and bonding quality.

Abstract: A semiconductor device (100) including a die (110) electrically connected to a substrate (120), wherein the substrate has a novel interconnect routing structure. The routing structure has a plurality of interconnects (122) including a plurality of intermediate vias (140), including both intermediate vias associated with supply interconnects and signal interconnects, that are clustered together to reduce undesirable mutual loop inductance (L.sub.m) and reduce switching noise (.DELTA.I). A plurality of first printed wires (128a) and a plurality of second printed wires (128b) may incorporated in the substrate for routing of the plurality intermediate vias in cluster form. The substrate may have a plurality of clusters of the intermediate vias.

Abstract: The specification describes interconnection layouts for chip-on-chip packages using solder bump interchip connections as vias between a single level metal interconnection pattern on the lower support IC chip and another single level interconnection pattern on the upper IC chip. This arrangement allows for the formation of air isolated crossovers of features on either chip.

Abstract: An aligned electronic circuit component assembly for attaching components onto larger mounting members at predetermined positions thereon are provided. The mounting or heat spreader members include shift resistant regions which are disposed in close proximity or substantially aligned with peripheral portions or edges of the component die when the die is placed in its predetermined position on an associated mounting or base member. The shift resistant regions can include non-linear edge surfaces, such as the edge surfaces around notches in the members, so as to provide areas on the base or heat spreader member which do not have solder thereon. It has been found that the surface tension of the liquid solder during reflow acts to provide a restraining force at the edge surfaces so as to restrain the electronic component from shifting from the desired position on the base member.

Abstract: An apparatus and method that permits the removal of heat from the back side surface of an integrated circuit semiconductor substrate while performing optical based testing through or at the back side surface of the semiconductor substrate.In one embodiment, the present invention includes a semiconductor device having an infrared transparent heat slug attached to the back side surface of the device. Heat is removed from the semiconductor device through an infrared transparent heat slug that is then thermally cooled by a conventional cooling technique.

Abstract: The semiconductor package including a semiconductor element 11 having a first face 21a and a second face 21b which is opposite to the first face 21a, an electrode 22 provided on the first face 21a, and a conductive lead 23 connected to the electrode 22 comprises an insulating film member 24 provided on the second face 21b for connecting the other end of the lead, the lead 23 is bent as oppose to a side face of the semiconductor element 11, and is connected each other with an elastic force between the electrode 22 and the film member 24, a bent part of the lead between the electrode 22 and the film member 24 turns to be a terminal part 23a. The circuit board has a connection means, connecting to the terminal unit 23a, and having an adequate size for placing the semiconductor package 11. The connection means is constituted of an accommodation groove part 46 or a frame part 50, and a plurality of pattern electrodes 47a, 47b, and the terminal part 23a is connected between the pattern electrodes 47a, 47b.

Abstract: To mount a semiconductor i.c. die on a support substrate the upper surface of the die is provided with electrically conductive bumps all of which are the same height. The bumps are provided on the ground connection pads on the upper surface of the die. The conductive pads on the die including the ground connection pads are connected to corresponding contacts on the upper surface of the substrate on which the die is mounted. Additionally, a thermally conductive, electrically conductive slug overlies the die and is mounted on and bonded to the bumps. The slug provides required heat removal from the die and also provides necessary ground connection to circuitry within the die.

Abstract: A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad.

Abstract: A semiconductor device includes (a) a semiconductor substrate, (b) a first interlayer insulating film formed on the semiconductor substrate, (c) a wiring layer having a thickness T and a width W1 greater than the thickness T formed on the first interlayer insulating film, the wiring layer being divided into a plurality of wiring layer segments each of which has a width W2 equal to or smaller than the thickness T, and (d) a second interlayer insulating film covering the wiring layer segments therewith. The semiconductor device ensures that even when a second interlayer insulating film is formed on a wiring layer by means of bias sputtering or bias CVD, projections are not formed on the second interlayer insulating film above the wiring layer. Namely, it is possible to completely planarize the second interlayer insulating film.

Abstract: There is provided a semiconductor integrated circuit chip including (a) a semiconductor substrate, (b) an insulating film formed on the semiconductor substrate, (c) first, second and third timing pulse signal lines each of which is formed of a common metal wiring layer and from which clock skew is generated, (d) an internal circuit to which the first, second and third timing pulse signal lines are electrically connected, (e) a first control signal line being designed to keep a high level while the internal circuit is in operation, and (f) a second control signal line being designed to keep a low level while the internal circuit is in operation.

Abstract: The invention is to a combination of a semiconductor device and a ground plane on a printed wiring board to provide a controlled impedance signal lead. A printed wiring board has a ground plane layer, and a semiconductor device having a down-set, or deep down-set, lead frame die mounting pad is mounted on the printed wiring board above the ground plane layer. The leads of the semiconductor device form a transmission line in combination with the ground plane, when the leads are placed a controlled distance above the ground plane.

Abstract: A getterer structure for dielectrically isolated wafer structures such as bonded wafers. The getterer is a layer of polysilicon along the sidewalls of semiconductor regions isolated from each other by trenches. The polysilicon may be doped. The polysilicon is oxidized and polysilicon deposited to fill voids in the trenches.

Abstract: Ta-Al-N is formed on a semiconductor device structure, such as a wiring line, to prevent interdiffusion between surrounding layers. The Ta-Al-N material serves as a diffusion between (i) two conductor layers, (ii) a semiconductor layer and a conductor layer, (iii) an insulator layer and a conductor layer, (iv) an insulator layer and a semiconductor layer, or (v) two semiconductor layers. Another use is to promote adhesion with adjacent layers, such as between (i) two conductor layers, (ii) a conductor layer and an insulator layer, (iii) a semiconductor layer and a conductor layer, or (iv) two semiconductor layers. The Ta-Al-N material also is used to form a contact or electrode. The Ta-Al-N material includes between 0.5% and 99.0% aluminum, between 0.5% and 99.0% tantalum, and between 0.5% and 99.0% nitrogen. The Ta-Al-N layer has a thickness between 50 angstroms and 6000 angstroms, and as part of a wiring line structure, has a thickness which is between 1% and 25% of the wiring line structure thickness.

Abstract: A lead frame and method of making the same are provided. The lead frame includes a die mounting portion, first and second pairs of tie bars, and first and second tie bar bridges extending between respective second extension portions of each tie bar pair. First and second pairs of tie bars are mechanically coupled to respective first and second ends of the die mounting portion. Each of the tie bars includes a first extension portion, a second extension portion, a tie bar span mechanically coupled to the first end of the die mounting portion via the first extension portion, a tie bar flap formed along a longitudinal reinforcement crease, and a lateral reinforcement portion extending from said first extension portion to said die mounting portion. The tie bar flap and the tie bar span lie in intersecting planes and are connected along the longitudinal reinforcement crease between the first extension portion and the second extension portion.

Abstract: A semiconductor device includes a device body including at least an LSI chip, and a lead structure having a base which is flexible and a plurality of pins which project from both sides of the base. The lead structure is integrated with the device body so that first ends of the plurality of pins are electrically connected to the LSI chip. The semiconductor device is manufactured in accordance with two steps of forming the lead structure and of integrating the lead structure with the deice body so that the first ends of the plurality of pins are electrically connected to the LSI chip.

Abstract: A cap that functions as a heat sink is affixed to the obverse surface of a semiconductor chip having ball bumps attached to the wiring pads on its surface, following which the semiconductor chip with the affixed cap is mounted on the bottom surface of a depression in a case and the opening of the depression in the case is simultaneously sealed by the cap.

Abstract: A semiconductor device is formed of stacked first and second semiconductor substrates each having internal circuits which are packaged within a package having a plurality of bump electrodes on the top and bottom principal planes. The bump electrodes on the top principal plane of the package are electrically connected to the internal circuits of the first semiconductor substrate and the bump electrodes on the bottom plane of the semiconductor substrate are electrically connected to the internal circuit of the second semiconductor substrate with the first and second semiconductor substrates arranged in mirror symmetry both physically with respect to each other and with respect to signals to be input into or output from the internal circuits. Module structures using a plurality of the semiconductor devices mentioned above are also described.

Abstract: A semiconductor chip is mounted on a die pad of a lead-frame, and the semiconductor chip mounted on the die pad is sealed in a plastic package; a side surface of the semiconductor chip and an exposed upper surface and a side surface of the die pad are covered with an organic stress relaxation layer so as to reduce a thermal stress due to the difference in thermal expansion coefficient between the semiconductor chip and the die pad, thereby presenting the plastic package from a crack.