Abstract: A method for forming an interconnect for semiconductor devices is provided. The interconnect includes raised contact structures covered with a conductive layer and having penetrating projections for penetrating contacts for the semiconductor devices. In an illustrative embodiment, the interconnect can be used to form a bi-substrate die. An interconnect substrate for the bi-substrate die includes control and logic circuitry and a memory substrate for the bi-substrate die includes a memory array. The interconnect can also be used to establish an electrical connection to microscopic contacts formed on a conventional die. In addition, the interconnect can be formed with three dimensional micro structures for contacting the microscopic contacts. Still further, the interconnect can be formed as wafer interconnect for electrically contacting dice contained on a wafer or for stacking multiple wafers.

Abstract: A semiconductor flip chip package is provided having a semiconductor flip chip integrated circuit device and a laminated substrate. The laminated substrate has a conductive core and at least one lamina formed on the core layer. Each lamina has a dielectric layer and a conductive layer. The dielectric layer is formed at least in part from a fluoropolymer material having disposed therein an inorganic filler material. At least one via extends through the at least one lamina. The via has an entrance aperature of <75 microns and an aspect ratio of between 3:1 and 25;1. The laminated substrate includes a plurality of individual pads to which the individual solder ball connections of the semiconductor flip chip integrated circuit device are connected.

Abstract: Electrode pads 6a are provided in the central portion of a semiconductor element 5, and the semiconductor element 5, which is mounted on a TCP tape 1 without device holes in this TCP tape, is mounted on the surface side of the TCP tape. In addition, the internal ends 2a of the wiring films 2 provided on the surface of the TCP tape 1 are extended all the way to the central portion of the semiconductor element 5 in conformity with these electrode pads 6a. The outside extension can be reduced and the TCP tape 1 shortened even when the wiring films 2 have the required length. In addition, the absence of device holes dispenses with the costs associated with punching out of the device holes, improves the mechanical strength of the wiring films 2, and enhances the holding force of the semiconductor element.

Abstract: A wired ceramic board has on a main surface of a ceramic substrate thereof a plurality of bonding pads each of which has a projection having a solderable outer surface and positioned inside an outer periphery of each bonding pad when observed in a plan view. To each bonding pad is bonded a solder ball by using solder which is lower in melting point than the solder ball. The ceramic board and a resinous printed board are placed one upon another in such a manner that their bonding pads are aligned with each other. The bonding pads are soldered together with low melting point solder. The projection of each bonding pad is embedded in or surrounded by a mass of low melting point solder and joined with the mass of solder to constitute an integral unit while serving as a core of the unit.

Abstract: Insulating resin layers are formed respectively so as to cover electrical pads for the purpose of connecting metal bumps of a semiconductor device and a mounting board, metal bump electrode pads being formed on the surface of these insulating resin layers, so that the electrode pads are electrically connected to one another. Thermal stress between the semiconductor device and the mounting board is absorbed by the insulating resin layers, the influence felt on the metal bumps being alleviated, thereby achieving an improvement in the reliability of the connection made by the metal bumps.

Abstract: A dual-inlaid damascene contact having a polished surface for directly communicating an electrically conductive layer to a semiconductor layer. A dielectric layer is formed on the electrically conductive layer. A dual-inlaid cavity is formed by etching a via cavity and a contact cavity into the dielectric layer. A damascene contact is formed by depositing tungsten into the dual-inlaid cavity. Chemical-mechanical polishing is used to planarize and smooth a surface of the damascene contact until the surface is coplanar with the dielectric layer. A semiconductor layer is then deposited on the damascene contact. The semiconductor layer can be the node of an amorphous silicon P-I-N photodiode. Electrical interconnection between the node of the photodiode and the electrically conductive layer is accomplished without using an intermediate electrode, and the smooth damascene contact improves surface adhesion, reduces contact resistance, and provides a discrete connection to the semiconductor layer.

Abstract: A multilayer micro circuit module, and the method of manufacturing same, comprises a number of green sheets of ceramic material which are sintered before any other fabrication steps are undertaken. The sintered sheets are then formed with registration holes and via, and an electrically conductive pattern formed of a noble metal or copper is deposited onto one or both major surfaces of each sintered sheets. The sintered sheets are stacked one on top of the other to form a stack whose exterior surface is coated with a sealing material such as solder or glass and then fired at a temperature less than the melting point of a metal forming the conductive patterns so that the interior of the stack including the conductive patterns is substantially isolated from contaminants.

Abstract: A structure and method is shown for measuring a plug and interface resistance values of an inter-layer contact structure in a semiconductor device. An inter-layer contact plug interconnects two metal layers in the semiconductor device forming a pair of plug to metal layer interfaces. A conductive trace is formed in an inter-metal dielectric layer between the metal layers, where the conductive trace couples the conductive plug to a pair of externally accessible pads. Each of the metal layers has a pair of pads. Using the pads coupled to the conductive trace, current is forced through each of the plug to metal interfaces and a voltage difference across each interface is measured in order to obtain the resistance of each interface. The total resistance of the inter-layer contact plug is similarly obtained and the resistance of the plug itself is obtained by subtracting the resistance of the two interfaces from the total resistance.

Abstract: A first polycide lead, which is formed on a silicon substrate, consists of a first doped polysilicon layer and a first tungsten silicide layer that is formed on the first doped polysilicon layer. An interlayer insulating film, which is formed on the silicon substrate, has an opening that reaches the first doped polysilicon layer. A second polycide lead, which is formed on the interlayer insulating film, consists of a second doped polysilicon layer that is connected to the first polycide lead in the opening and a second tungsten silicide layer that is formed on the second doped polysilicon layer. In the opening, the first and second doped polysilicon layers are in contact with each other at the side surfaces of the first polycide lead.

Abstract: A non-destructive-readout nonvolatile semiconductor diode switching device that may be used as a memory element is disclosed. The diode switching device is formed with a ferroelectric material disposed above a rectifying junction to control the conduction characteristics therein by means of a remanent polarization. The invention may be used for the formation of integrated circuit memories for the storage of information.

Abstract: An electronic module for data carriers having at least one integrated circuit includes an electrically conductive layer with contact surfaces for communication of the circuit with external devices and having an insulated layer which is connected to the conductive layer and has recesses for electrically connecting the contact surfaces with the circuit. Each recess protrudes partly into the contact surface adjacent the recess. The recesses may be formed in such a way that the area of insulating layer remaining in the center of the module takes up substantially only the integrated circuit surface.

Abstract: A thin film field effect transistors and manufacturing method for the same are described. The channel region of the transistor is spoiled by an impurity such as oxygen, carbon, nitrogen. The photosensitivity of the channel region is reduced by the spoiling impurity and therefore the transistor is endowed with immunity to illumination incident thereupon which would otherwise impair the normal operation of the transistor. The spoiling impurity is not introduced into transistors which are located in order not to receive light rays.

Abstract: A semiconductor package is provided that includes a semiconductor chip that is mounted on a mount board with metal bumps interposed therebetween so as to create a gap. A structure is provided in the gap for limiting the flow of a resin, which is deposited along side the semiconductor chip, around the peripheral portion of the semiconductor chip. The structure increases the resistance to the flow of the resin in the peripheral portion of the semiconductor chip. Therefore, the rate at which the resin flows in the peripheral portion of the semiconductor chip is made lower than the rate at which the resin flows near the central portion of semiconductor chip. Accordingly, the formation of a resin-less void in the gap is suppressed so that the grade and quality of the semiconductor device is improved. In one embodiment, the structure in the gap includes projections provided on a portion of the mount board that corresponds to the peripheral portion of the semiconductor chip.

Abstract: A surface mount semiconductor laser diode package has a substrate on which the laser diode is mounted. The top electrode of the laser diode is wire-bonded to the top end of a plated-through conduit through the substrate, and the bottom end of the plated-through conduit is connected to a circuit contact plated at the bottom surface of the substrate. The bottom electrode of the laser diode is flip-chip mounted to the top end of another plated-through conduit, and bottom end of the second plated-through conduit is connected to a second circuit contact. Each laser diode is covered with a transparent lid or a lid with a lens. For mass production, a large number of the laser diodes arranged in a matrix formation are mounted on a common substrate. Walls are erected around each laser diode. A transparent cover is placed over the walls. All the plated-through conduits at the edges of the laser diodes in a same column are aligned and sawed through together.

Abstract: A semiconductor device package is presented having signal traces interposed between power and ground conductors in order to form stripline transmission lines. The semiconductor device package includes a substrate having a die area defined upon an upper surface. The die area is dimensioned to receive the integrated circuit. A first planar conductive layer formed upon the upper surface includes a first set of bonding pads and a set of conductive traces. Members of the first set of bonding pads are arranged upon the upper surface proximate the die area, and are used to make electrical connections to the integrated circuit. Members of the set of conductive traces are connected between one of two polarities of a power supply and corresponding members of the first set of bonding pads, and function as reference planes for underlying signal traces. A second planar conductive layer is positioned between the first planar conductive layer and an underside surface of the substrate.

Abstract: Apparatus and method of increasing the distance of the gap between a lead frame and a semiconductor die surface in a package assembly. An adhesive layer and a gap increasing layer are disposed between the lead frame and the semiconductor die surface. The gap increasing layer has a thickness selected to reduce likelihood of package particles from being trapped between the lead frame and the die surface. The gap increasing layer includes silver plating, and has a thickness of at least about 300 to 500 microinches.

Abstract: A semiconductor device comprising an insulating film at least partially containing a fluorine-containing film, formed above a semiconductor substrate, and a titanium nitride film formed on the insulating film. The above titanium film functions as a barrier metal film for barriering the diffusion of fluorine (F) atoms.

Abstract: The present invention discloses a chip-size package (CSP) ready multiple chip module (MCM) board having a top surface and a bottom surface for mounting and packaging a plurality of integrated circuit (IC) chips on the top surface. The MCM board is provided with a plurality of chip connection terminals on the top surface for electrically connecting to the IC chips. The MCM board further includes a plurality of via connectors in electrical connection with each of the MCM connection terminals. The MCM board further includes a plurality of CSP connection terminals disposed on the bottom surface substantially under the IC chips wherein each of the via connectors penetrating the MCM board for electrically connecting the CSP connection terminals to the MCM connection terminals.

Abstract: A semiconductor package (110) includes a tape substrate (135) having a top surface, a bottom surface, a plurality of conductive metal traces (115) formed on the top surface and a plurality of holes (130) arraigned in an array pattern formed through the tape substrate (135) exposing the conductive traces (115) from the bottom surface. A nonconductive metal plate or stiffener frame (155) attached to the bottom surface of the tape substrate (135) to support the tape substrate (135) during assembly. The stiffener frame (155) having through holes (160) corresponding to the holes (130) in the tape substrate (135) and being made from anodized aluminum, thus making it electrically nonconductive. An integrated circuit (IC) chip (120) is mounted on the top surface, opposite the stiffener frame (155).

Abstract: A technique to form a structure with a rough topography (415) in a planarized semiconductor process. The rough topography (415) is formed by creating cored contacts (433). Subsequent process layers may be further stacked on top of the cored contacts in order to augment the nonplanar characteristics of the cored contacts. This rough topography structure may be used to align integrated circuits and wafers. An integrated circuit may be laser aligned using this alignment structure.