Abstract: A microelectronic component for mounting a rigid substrate, such as a hybrid circuit to a rigid support substrate, such as a printed circuit board. The microelectronic component includes a rigid interposer which may have a chip mounted on its first surface; a pattern of contacts on the rigid interposer; a flexible interposer overlying the second surface of the rigid interposer; a pattern of terminals on the flexible interposer; flexible leads; and solder coated copper balls mounted on the flexible interposer. The microelectronic component may have a socket assembly mounted on the first surface of the rigid interposer. The microelectronic component may be mounted on a rigid support substrate.

Abstract: A barrier material deposited as a barrier film layer in a semiconductor device to reduce the interdiffusion of materials of varying electrical conductivity comprising adjacent layers in a semiconductor device is provided. The barrier material contains a transition metal, aluminum, silicon and nitrogen as essential ingredients. Suitable transition metals are tantalum and titanium. The material provides excellent resistance to diffusion across the range of temperatures occurring in an integrated circuit manufacturing process. The material also exhibits good adhesion to materials used in semiconductor processes.

Abstract: Disclosed is a semiconductor package where at least one tie bar is arranged on the leadframe such that the die to be packaged is attached to the tie bar by binding tape. The problem of gap or delamination will not occur due to the disuse of silver epoxy and die paddle. The processing time can be reduced and the applicability to die is enhanced.

Abstract: A shielding apparatus for an electronic component includes a first insulative encapsulant surrounding at least a portion of the component and a second encapsulant surrounding said first encapsulant and having conductive particles dispersed therein for absorbing ionizing radiation.

Abstract: A circuit board surface treatment equipment, which includes an upper solution chamber and a bottom solution chamber defined within a machine base at different elevations, a set of conveying rollers and upper and lower bumper rollers arranged in the upper solution chamber and controlled to deliver circuit boards through the upper solution chamber for treatment, upper and lower pressure-balanced water knives respectively mounted in gaps in between the conveying rollers and controlled to eject a surface treatment solution onto the circuit boards, and water level control switch means which open the passage between the upper solution chamber and the bottom solution chamber for letting the surface treatment solution flow from the upper solution chamber to the bottom solution chamber when the level of surface treatment solution in the upper solution chamber surpasses a predetermined high level.

Abstract: A semiconductor device having multiple layers uses different size contacts at different layer in order in order to simplify the manufacturing process and the depth of etching required. Contact sizes are selected based on the responsiveness of the material to the etching process. Where a deep etch is required, a larger contact is used. A shallower etch through similar material uses a smaller contact to slow the etching process. As a result, the etches can complete at about the same time. The technique can be employed to etch any number of contacts. An intermediate size contact can be used where the material to be etched results in a slower etching process. A plurality of contact sizes can be used depending on the depths of etching required and the characteristics of material to be etched, so that the etching for all the contacts completes at substantially the same time.

Abstract: In an epoxy resin composition comprising an epoxy resin, a curing agent, and at least 70% by weight of an inorganic filler, at least one of the epoxy resin and the curing agent has such a molecular weight distribution as to provide an average dispersity Mw/Mn of less than 1.6, a two-nucleus compound content of less than 8% by weight and a seven- and more-nucleus compound content of less than 32% by weight. When the composition is cured at 180.degree. C. for 90 seconds into a primary product having Tg1 and the primary product postcured at 180.degree. C. for 5 hours into a secondary product having Tg2, the relationship: (Tg2-Tg1)/Tg2<0.1 is satisfied. The composition is fast-curing and effectively moldable and cures into a reliable product without a need for postcure.

Abstract: One embodiment of the present invention is an electronic assembly which may have a first integrated circuit package mounted to a first side of a substrate and a second integrated circuit package mounted to a second side of the substrate. A thermal plate may be thermally coupled to the first integrated circuit package. A heat sink may be mounted to the thermal plate. A thermal bus may be is thermally coupled to the second integrated circuit package and the thermal plate. The thermal bus bar allows heat to flow from the second integrated circuit package to the thermal plate and heat sink. The electronic assembly of the present invention can thus remove heat from integrated circuit packages located on both sides of a substrate with only one heat sink.

Abstract: An electronic circuit having: a substrate with an upper surface; a lower level wiring made of conductive material and disposed on the substrate; an insulating cover film covering the surface of the lower level wiring; an interlayer insulating film formed on the substrate, covering the insulating cover film; an opening formed through the interlayer insulating film and the insulating cover film at an interlayer contact region extending from an area corresponding to the inside region, as viewed in the in-plane layout of the substrate, of the lower level wiring to an area corresponding to the outside region of the lower level wiring; and a higher level wiring disposed on a partial region of the interlayer insulating film and in the interlayer contact region, the higher level wiring being electrically connected to the lower level wiring in the interlayer contact region.

Abstract: A semiconductor apparatus includes a semiconductor chip and a die pad on which the semiconductor chip is mounted. The die pad is provided thereon with an opening. The semiconductor chip and the die pad may be shaped to be similar figures of rectangle, and the opening may include a plurality of first slits which are arranged around the corners of the die pad, respectively.

Abstract: A semiconductor wafer, a semiconductor device, and a method of manufacturing the semiconductor device which prevent corrosion of pads in a semiconductor integrated circuit. A semiconductor wafer having semiconductor integrated circuits and interconnections extending from wire-bonding pads on the semiconductor integrated circuits to a dicing line is cut along the dicing line into chips. Part of the interconnections are left on the chips as wafer testing pad remainders, and the surfaces of the wafer testing pad remainders are covered with an insulating film, preventing the invasion of water from the wafer testing pad remainders and corrosion of the wire-bonding pads in the semiconductor integrated circuit, improving reliability and durability of the semiconductor device.

Abstract: A semiconductor device includes a semiconductor substrate having a main surface, and a multi-layered wiring layer formed on the main surface of the semiconductor substrate, the multi-layered wiring layer having a plurality of wiring layers insulatively laminated, wherein the melting points of the plurality of wiring layers are set gradually lower in a direction towards the higher-level side.

Abstract: Two or more bonding option pads are aligned in a predetermined direction on a semiconductor chip. Leads on higher and lower potential sides are provided on both sides of the bonding option pads such that the leads are extended in the direction passing across the predetermined direction. At least one of the bonding option pads is connected to at least one of the leads by means of a bonding wire.

Abstract: A condensed memory matrix is fabricated by conductively connecting the attachment bumps of a substrate with the attachment bumps of a wafer of DRAM chips and physically bonding the juxtaposed surfaces of the substrate and the wafer with a dielectric curable resin. An array of heat fins is bonded to the inactive surface of the wafer by a thermally conductive curable resin.

Abstract: In a lead frame, inside inner leads are supported by supporting leads through an insulator. The inside inner leads and outside inner leads are separated from one another and are doubly arranged. In manufacturing a semiconductor device by using this lead frame, a semiconductor chip is mounted on the insulator, and the semiconductor chip is connected with the inside inner leads and the outside inner leads through metal wires, and the resultant is sealed with a resin. Thus, projections provided on the bottoms of the inside inner leads and the outside inner leads can work as external terminals. Since the external terminals can be disposed two-dimensionally on the bottom, the lead frame is applicable to high density packaging and multi-pin devices, and can additionally provide a so-called burr-less structure free from uncut waste of the resin.

Abstract: An inventive Leads-Over-Chip (LOC) lead frame includes an assembly of interdigitated leads constructed to overlie double-sided adhesive tape on the front-side surface of an integrated circuit (IC) die. An attachment surface of each lead is adhesively attachable to the tape, and at least some of the leads are constructed to extend across the front-side surface of the die from one edge substantially to another edge, such as an adjacent or opposing edge. As a result, a substantial area of the front-side surface of the die is adhesively attachable to the leads through the tape, so the die is supportable in an IC package in an improved manner, and the heat may be conducted away from the die through the lead frame in an improved manner.

Abstract: A semiconductor package and a socket thereof that are easily adaptable to a multiple pin structure includes a nonconductive base layer, a plurality of conductive metallic leads that extend vertically through the base layer, a wiring layer in which a pattern of fine metallic wires are formed to electrically couple to the conductive metallic leads to a semiconductor chip mounted in the package, a recess formed in the central portion of the wiring layer, and a cover for closing the upper portion of the recess. A semiconductor chip is mounted on the bottom portion of the recess, and conductive wires electrically couple the semiconductor chip to the fine metallic wires of the wiring layer.

Abstract: An electronic cartridge. The cartridge may include a first cover and a second cover that are adjacent to a substrate. One or more integrated circuit packages may be mounted to the substrate. The cartridge may include a pin that extends from the first cover and which has a barb that is embedded into the second cover. The embedded barb will damage the second cover if the cover is removed from the cartridge. The present invention thus prevents the removal and re-installation of the cover from the cartridge.

Abstract: A semiconductor device and fabrication method are presented which employ a thermally conductive substrate having an outer layer of palladium. The substrate may be made of, for example, a metal such as copper. The substrate does not itself include layers of signal traces or bonding pads which function as device terminals, but provides a stiff backing for support of a flexible circuit which includes signal traces and bonding pads. An adhesive layer bonds the flexible circuit to the substrate. The outer layer of palladium has a desired surface roughness and chemical properties which improve the adhesion of the adhesive layer to the substrate. The substrate has opposed, substantially planar upper and underside surfaces. In one embodiment, the underside surface of the substrate has a die cavity, and the flexible circuit includes a set of conductors bonded to one side of a sheet of dielectric material (e.g., polyimide film).

Abstract: In order to package an electronic component, a leadframe is provided having at least one flag portion (2) and at least one lead portion (7) extending towards the flag portion (2). The lead portion (7) includes an end portion (10) of reduced thickness adjacent the flag portion (2) and a channel (9) between the end portion (10) and the rest of the lead portion. The leadframe is etched to form the channel (9) and the end portion(10), which together form a locking step. The electronic component (3) is then mounted on the flag portion (2) and electrically connected to the end of the lead portion (7). The electronic component (3), the electrical connection (5), at least the end portion (10) and the intermediate portion (9) of the lead portion (7) and at least part of the flag portion (2) are encapsulated in a plastics molding compound, which enters and fills the locking step, and is then cured.