Patents Examined by Jigar Patel
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Patent number: 9507669Abstract: A method of data transmission using HARQ is provided. The method includes transmitting an uplink data, receiving an ACK/NACK signal for the uplink data, keeping the uplink data in a HARQ buffer when the ACK/NACK signal is an ACK signal, and retransmitting the uplink data when an uplink scheduling information for retransmission of the uplink data is received. In the present invention, a transmission error in an ACK/NACK signal is promptly detected, and thus data can be transmitted at a high speed.Type: GrantFiled: July 21, 2008Date of Patent: November 29, 2016Assignee: LG Electronics Inc.Inventors: Doo Hyun Sung, Hyung Ho Park, Jin Soo Choi, Jae Hoon Chung, Jong Young Han, Kyu Jin Park, Eun Jong Lee, Han Gyu Cho
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Patent number: 9496051Abstract: Provided is a control device for managing a plurality of memory channels driven through multichannel interleaving. The apparatus includes a stripe configuring unit for configuring a stripe according to a physical number of pages included in the plurality of memory channels, and a parity generating unit for generating parity data on the configured stripe.Type: GrantFiled: February 8, 2013Date of Patent: November 15, 2016Assignee: TLI INC.Inventors: Jae Ho Kim, Jong Min Lee, Jong Moo Choi, Dong Hee Lee, Sam Hyuk Noh
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Patent number: 9454445Abstract: The virtual computer of the active system includes a memory configured of small regions grouped in a first group and small regions grouped in a second group. When a checkpoint is detected by the checkpoint detection unit, the transfer control unit suspends the virtual computer, copies, to a transfer buffer (not shown), data of the small regions in the first group among the small regions of the memory having been updated after a previous checkpoint, and after inhibiting writing to the small regions in the second group, restarts the virtual computer. Further, the transfer control unit copies data of the small regions, in which writing is inhibited, to the transfer buffer and releases write inhibit, and transfers the data of the small regions, having been copied to the transfer buffer, to the physical computer.Type: GrantFiled: March 11, 2014Date of Patent: September 27, 2016Assignee: NEC CORPORATIONInventor: Hiroaki Miyajima
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Patent number: 9454418Abstract: A method for testing processors includes generating, from a set of input bits, a first set of machine data bits in a first processor and a second set of machine data bits in a second processor dissimilar to the first processor, and comparing the first and second sets of machine data bits to output a first comparison result. The method also includes generating, from a third set of machine data bits, a first and second sets of machine result bits, and comparing the first and second sets of machine result bits to output a second comparison result. The method further includes generating, from a fourth set of machine data bits, a first and second sets of output bits, and comparing the first and second sets of output bits to output a third comparison result. The method also includes determining whether the first and second processors operate substantially similar to each other based on at least one of the first, second, and third comparison results.Type: GrantFiled: August 21, 2014Date of Patent: September 27, 2016Assignee: ROCKWELL COLLINS, INC.Inventors: Mark A. Kovalan, Mark Clifford Singer
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Patent number: 9436541Abstract: Dynamic service-event management methods to implement a dynamic service-event management system. Generally applicable in fields of utility, telecommunication and financial service providers. Therein, events has affect to status or quality of service projecting to service in two steps and using common-format events. In first step, external source originated events (11, 21, 24) are converted in network parser module(s) (1, 2) to a common event-format. In second step, the common format events (12, 22) are processed and their information projected to a service in a service parser module (3). The resulting common format service-event (31) and network events (13, 23) are stored by an alert parser module (4). The stored events are accessible for other connected systems through a database based application programming interface (41). Opening times are effectively handled using opening events (61). A bearer-to-beared object assignment can be handled in two ways.Type: GrantFiled: December 19, 2014Date of Patent: September 6, 2016Assignee: KNI Muszaki Tanacsado Kft.Inventors: Zsolt Kendi, Istvan Paroczai
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Patent number: 9430312Abstract: The system includes an analyzer that analyzes a sample, or a processing device that pre-processes the sample, and a management device that manages at least one of the analyzer and the processing device, wherein the management device includes: error detection means that detects errors in the analyzer or the processing device; storage means having stored therein an operator notification management table in which at least one operator is registered per kind of error; error notification means that notifies an error that the error detection means has detected to operators who are to individually handle the error, the means notifying on the basis of the operator notification management table and in accordance with the kind of error detected by the error detection means; and registration means that registers an operator, who has handled the error as a troubleshooter, among operators to whom the error was notified from the error notification means.Type: GrantFiled: October 23, 2012Date of Patent: August 30, 2016Assignee: Hitachi High-Technologies CorporationInventor: Naomi Ishii
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Patent number: 9430355Abstract: A thread dump analysis tool analyzes a series of thread dumps and identifies one or more potential problems in the application from which the thread dumps were generated. Hints regarding the potential problems are presented. The hints can be generated based on relative values generated by analysis of sequential dumps. The hints may be hints that could not be generated by analysis of a single thread dump. Other hints may be hints that are enhanced by analysis of multiple thread dumps, whose importance is made clearer by appearance in multiple thread dumps, or that are unchanged in detection, importance, or both, by the use of multiple thread dumps. The hints can then be presented in order of importance. Additionally or alternatively, hints below a certain threshold of importance can be hidden.Type: GrantFiled: September 18, 2014Date of Patent: August 30, 2016Assignee: SAP SEInventors: Matthias Braun, Dietrich Mostowoj, Ralf Schmelter, Thomas Klink, Steffen Schreiber, Johannes Scheerer, Michael Wintergerst
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Patent number: 9424165Abstract: Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, a forced halt sequence can be initiated, which causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor state at the time that the hung transaction was dispatched, which can be viewed during debug mode to facilitate determining a cause of the hung transaction.Type: GrantFiled: March 14, 2013Date of Patent: August 23, 2016Assignee: APPLIED MICRO CIRCUITS CORPORATIONInventors: Waseem Kraipak, Sukanto Ghosh
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Patent number: 9417940Abstract: An operations management system includes a correlation model storing unit, an analysis order storing unit, an analysis unit, and an order control unit. The correlation model storing unit stores a correlation model which indicates a correlation among plural types of performance values, for each of plural systems. The analysis order storing unit stores a detection order in the plural systems for carrying out detection of correlation destruction. The analysis unit carries out, in each of plural time periods, detection of whether the correlation destruction of the correlation included in the correlation model of each of the plural systems is caused or not by use of performance values inputted for the each of plural time periods, on the basis of the detection order. The order control unit updates the detection order in the each of plural time periods.Type: GrantFiled: March 21, 2012Date of Patent: August 16, 2016Assignee: NEC CorporationInventor: Yosuke Nonogaki
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Patent number: 9411701Abstract: An apparatus relating generally to a system-on-chip is disclosed. In this apparatus, the system-on-chip has at least one analog block, an input/output interface, a data test block, and a processing unit. The processing unit is coupled to the input/output interface to control access to the at least one analog block. The data test block is coupled to the at least one analog block through the input/output interface. The processing unit is coupled to the data test block and configured to execute test code having at least one test pattern. The data test block under control of the test code executed by the processing unit is configured to test the at least one analog block with the test pattern.Type: GrantFiled: March 13, 2013Date of Patent: August 9, 2016Assignee: XILINX, INC.Inventor: Sarosh I. Azad
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Patent number: 9396058Abstract: Methods, systems, and computer-readable media for detecting errors within a system by using behavior profiles are presented. At a first time, user requests may be received and serviced. The serviced user requests may be logged. Based on the logged user requests, profiles may be determined. At a second time, user requests may be received and serviced. The serviced user requests may be logged. The logged serviced user requests may be compared to the profiles determined at a first time. For example, the determined profiles may include an error rate for serviced user requests. At the second time, an error rate for the logged serviced user requests may be compared to an error rate included the determined profiles. Serviced users requests may be flagged based on the comparison.Type: GrantFiled: February 2, 2016Date of Patent: July 19, 2016Assignee: Bank of America CorporationInventors: John R. Sampson, David L. Yommer
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Patent number: 9384078Abstract: A method for diagnosing a mechanism of untimely cut-offs of the power supply to a motor vehicle computer (1) which is programmed to execute a startup routine when woken up and a shutdown routine before being put into sleep mode, includes, at the time of each shutdown routine, generating and storing in storage elements a marker representing a completed execution of the shutdown routine, and at the time of each startup routine, checking for the presence of a marker, and if the marker is present, reinitializing the storage elements of the marker, and if the marker is absent, generating a data element representing a power supply fault.Type: GrantFiled: July 19, 2013Date of Patent: July 5, 2016Assignees: CONTINENTAL AUTOMOTIVE FRANCE, CONTINENTAL AUTOMOTIVE GMBHInventor: Stephane Eloy
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Patent number: 9372774Abstract: A redundant computing architecture includes a first control unit, a second control unit, and a switch. The first control unit is configured to provide a first control signal in response to a sensory input and is further configured to provide a health status indicator that is indicative of a fault condition within the first control unit. Additionally, the second control unit is configured to provide a second control signal in response to the sensory input. Each of the first and second control signals is respectively operative to control an actuator. The switch is configured to: receive the health status indicator, the first control signal, and second control signal; provide the first control signal to the actuator if this health status indicator does not indicate a fault: and provide the second control signal to the actuator if this health status indicator does indicate a fault.Type: GrantFiled: May 22, 2013Date of Patent: June 21, 2016Assignee: GM Global Technology Operations LLCInventor: Joseph G. D'Ambrosio
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Patent number: 9367407Abstract: Embodiments of the present invention provide systems, methods, and computer program products for optimizing a placement plan. In one embodiment, a method is disclosed in which a request for registration with an external advisor is received. A time to live is received from each external advisor and used to determine an overall timeout period value for a placement engine. After receiving a predictive failure alert, internal and external advisors are ranked according to criteria and advice is received from the qualified advisors. A placement plan is generated based on the advice received from the advisors.Type: GrantFiled: August 5, 2014Date of Patent: June 14, 2016Assignee: International Business Machines CorporationInventors: Pradipta K. Banerjee, Ashish Billore, Sudipta Biswas, Muthu A. Muthiah
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Patent number: 9367405Abstract: A method is used in managing software errors in storage systems. It is detected that a first processor of a storage system has a problem performing an I/O on a logical object. The first processor has a first path to the logical object. The problem includes a software error. Whether responsibility of performing the I/O on the logical object is transferred to a second processor of the storage system is evaluated. The second processor has a second path to the logical object.Type: GrantFiled: March 14, 2013Date of Patent: June 14, 2016Assignee: EMC CorporationInventors: Robert P. Foley, Peter Puhov, Marc C. Cassano, Daniel E. Cummins, David W. Harvey
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Patent number: 9367408Abstract: Embodiments of the present invention provide systems, methods, and computer program products for optimizing a placement plan. In one embodiment, a method is disclosed in which a request for registration with an external advisor is received. A time to live is received from each external advisor and used to determine an overall timeout period value for a placement engine. After receiving a predictive failure alert, internal and external advisors are ranked according to criteria and advice is received from the qualified advisors. A placement plan is generated based on the advice received from the advisors.Type: GrantFiled: October 9, 2014Date of Patent: June 14, 2016Assignee: International Business Machines CorporationInventors: Pradipta K. Banerjee, Ashish Billore, Sudipta Biswas, Muthu A. Muthiah
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Patent number: 9361201Abstract: According to one embodiment, a memory system includes a NAND-type flash memory and a memory controller. The memory controller includes a monitoring module and a determination module. The monitoring module acquires an elapsed time from the start of data erase of a first block in the NAND-type flash memory. The determination module determines whether the elapsed time has exceeded a reference time before completion of the data write in the first block.Type: GrantFiled: January 24, 2013Date of Patent: June 7, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yoko Masuo, Hironobu Miyamoto
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Detecting potential class loader problems using the class search path sequence for each class loader
Patent number: 9355011Abstract: A method, system and computer program product for identifying potential class loader problems prior to or during the deployment of the classes to the production environment. A set of class loaders is loaded into memory. The set of class loaders is arranged hierarchically into parent-child relationships. The class search path sequence for each class loader in the hierarchy is generated to detect and identify potential class loader problems. Those class loaders with a duplicate class in its class search path sequence are identified as those class loaders that may pose a potential problem. A message may then be displayed to the user identifying these class loaders as posing a potential problem. By identifying these class loaders prior to or during the deployment of the classes to the production environment, class loader problems may be prevented from occurring.Type: GrantFiled: June 9, 2014Date of Patent: May 31, 2016Assignee: International Business Machines CorporationInventor: Jinwoo Hwang -
Patent number: 9355020Abstract: Methods, systems, and computer-readable storage media for resolving nondeterminism in a behavior model of a computing system under test (SUT). In some implementations, actions include: receiving a behavior model relating to a SUT, the behavior model including two or more nondeterministic transitions; obtaining trace data associated with execution of the SUT across the two or more nondeterministic transitions; determining based on the trace data, two or more transition guards that resolve nondeterminism of the two or more nondeterministic transitions; and associating the two or more transition guards with the two or more nondeterministic transitions to provide an extended behavior model.Type: GrantFiled: July 22, 2014Date of Patent: May 31, 2016Assignee: SAP SEInventors: Matthias Schur, Andreas Roth
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Patent number: 9354996Abstract: The present invention relates to a system test apparatus. The system test apparatus includes an insertion module configured to insert a test agent into a process control block, a hooking module configured to hook a test target to a test code using the test agent when an event related to the test target occurs, a scanning module configured to collect pieces of test information about a process in which the event related to the test target has occurred when the test target is hooked, and a logging module configured to store the pieces of test information collected by the scanning module.Type: GrantFiled: March 15, 2011Date of Patent: May 31, 2016Assignees: Hyundai Motor Company, Kia Motors Corporation, Ehwa University Industry Collaboration FoundationInventors: Byoung Ju Choi, Joo Young Seo, Sueng Wan Yang, Jin Yong Lim, Young Su Kim, Jung Suk Oh, Hae Young Kwon, Seung Yeun Jang