Abstract: Stackable Layer 2 switches may be upgraded through a stateless upgrade procedure that minimizes software upgrade complexity while leveraging the intrinsic redundancy of the network to minimize traffic disruption. Disclosed methods may be targeted to platforms that lack support for other non-disruptive upgrade technologies, but that can leverage the intrinsic network redundancy to minimize traffic impact during a stack upgrade.

Abstract: A method and apparatus are described for protecting real time media including receiving media packets, generating media bit strings from the media packets, applying a forward error correcting code across the generated media bit strings to generate at least one forward error correcting bit string and generating at least one forward error correcting packet from the at least one forward error correcting bit string. Also described are a method and apparatus for recovering from losses of real time media packets including forming media bit strings from received media packets, forming forward error correcting bit strings from received forward error correcting packets, decoding the formed media bit strings and forward error correcting bit strings to obtain recovered media bit strings and recover lost media packets from the recovered media bit strings. Further described is a data structure for a forward error correcting header on computer readable media.

Abstract: In order to rapidly perform verification processing on the basis of test patterns in a circuit to be verified, an emulator verification system comprises: an emulator verification device that verifies the normality of content to be executed on the basis of verification test information in a circuit to be verified; a moveable test pattern storage device that is connected to the emulator verification device in an attachable/detachable manner, and that inputs test information for verification processing having a larger volume than a preset data volume into the emulator verification device; and a moveable result pattern storage device that connects to the emulator verification device in an attachable/detachable manner, and that acquires and stores verification results information having a larger volume than a fixed data volume, which shows the results of the verification processing in the emulator verification device.

Abstract: A system and method for partial fault tolerance in an embedded appliance is disclosed. The method comprises providing an embedded appliance having first and second digital storage locations, with the second location including a boot manager and a recovery operating system. An image instance of the operational section of the first digital storage location can be copied at a selected frequency to a selected location on the second digital storage location. Files in the image instance can be re-mapped to operate at the second digital storage location. The embedded appliance can be rebooted from the second digital storage location using the boot manager to load an operating system in the image instance to operate the embedded appliance from the image instance at the selected location on the second digital storage location when the operational section of the first digital storage location is inaccessible.

Abstract: A method, computer program product, and system for de-centralized stream processing is provided. The method may include providing a plurality of processing nodes in a hierarchical genome having a plurality of levels, wherein each of said processing nodes is configured to transmit and receive a stream of data. The method may further include restricting a subset of the plurality of processing nodes from differentiating into a role within each level of the hierarchical genome. The method may also include identifying a failure at one of the processing nodes and replacing the failed node with one of the processing nodes from the restricted subset.

Abstract: Systems and methods are disclosed herein for a replicated duplex computer system. The system includes a triplet of network elements, which each maintain a clock signal, and a monitor at each network element for monitoring incoming clock signals. Each network element interfaces with a fault containment region (FCR). The system provides the ability to transition to a duplex system if one of the fault containment regions fails. The three network elements are able to send their clock signals to the other network elements and receive their own clock signal and clock signals from the other elements. The monitors are configured to detect discrepancies in the clock signals of the network elements. If a monitor determines that an FCR has failed, each network element is reconfigured so that the FTPP system operates in a duplex mode without the faulty FCR by replacing the clock signal from the faulty element with its own clock signal.

Abstract: A method (500) or a diagnostic recording device (400) having transactional memory and a processor coupled to the transactional memory can store (502) contents of a transaction log (40) of the transactional memory, detect (504) an exception event, and replay (506) last instructions that led up to the exception event using a debugger tool (80). The transactional memory can be hardware or software based transactional memory. The processor can also store the transaction log by storing the contents of the transaction log in a core file (302) which can include a stack (60), a register dump (70), a memory dump (75), and the transactional log. The debugger tool can be used to load up the core file, an executable file (95), and a library (90) to enable the diagnostic recording device to retrace transactions occurring at the diagnostic recording device up to the exception event.

Abstract: A test controller translates test rules into executable code and validates the test results using the executable code. The test controller translates the test rules using a test grammar. The test rules are used to indicate expected test results of a device under test. The test controller further generates the test results by executing test instructions. In addition, the test controller uses the test grammar to validate the test rules.

Abstract: Trace circuitry for monitoring a behavior of at least one processor and for generating items of trace data indicative of processing activities of said at least one processor executing a stream of instructions is disclosed. The stream of instructions comprises different types of instructions, each type specifying a different operation, at least one type of instruction comprising a multiple transfer instruction specifying a plurality of data transfers.

Abstract: A circuit includes a circuit identification storage module and a control module. The circuit identification storage module stores circuit identification information. The control module receives the circuit identification information and in response thereto selectively performs a secure boot procedure or a test boot procedure. The control circuit performs the secure boot procedure when the circuit identification information indicates that the circuit is a production circuit. The control circuit performs the test boot procedure when the circuit identification information indicates that the circuit is a test circuit. A related method is also disclosed.

Abstract: A semiconductor chip is described having different instances of cache agent logic circuitry for respective cache slices of a distributed cache. The semiconductor chip further includes hash engine logic circuitry comprising: hash logic circuitry to determine, based on an address, that a particular one of the cache slices is to receive a request having the address, and, a first input to receive notice of a failure event for the particular cache slice. The semiconductor chip also includes first circuitry to assign the address to another cache slice of the cache slices in response to the notice.

Abstract: System, method and computer program product for scheduling threads in a multiprocessing system with selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). The method configures the selective pairing facility to use checking provide one highly reliable thread for high-reliability and allocate threads to corresponding processor cores indicating need for hardware checking. The method configures the selective pairing facility to provide multiple independent cores and allocate threads to corresponding processor cores indicating inherent resilience.

Abstract: An integrated circuit including a logic analyzer with enhanced analyzing and debugging capabilities and a method therefor. In one embodiment of the present invention, an embedded logic analyzer (ELA) receives a plurality of signals from a plurality of buses within an integrated circuit (IC). The ELA includes an interconnect module to select a trigger signal and/or a sampled signal from the plurality of received signals. A trigger module sets at least one trigger condition and detects if the trigger signal satisfies the at least one trigger condition. When the trigger condition is satisfied, an output module performs at least one task based upon the satisfied at least one trigger condition. If a sampling process is initiated by the output module, the plurality of sampled signals is sampled and may be stored in a memory. The capability of the output module to perform multiple user-defined tasks enhances the debugging capability of the ELA and makes it more versatile.

Abstract: A microcomputer or microcontroller with a watchdog timer-counter also has an external reset signal generator. When the central processing unit of the microcomputer or microcontroller fails to execute its control program correctly, the watchdog timer-counter generates an internal reset signal for a first interval, resetting the central processing unit, and the external reset signal generator generates an external reset signal for a second interval, different from the first interval. The length of the second interval can be set to match the requirements of external peripheral devices to which the external reset signal is supplied.

Abstract: An image reproduction apparatus including a power control unit detecting whether an error has occurred in supplying power to the image reproduction apparatus; and a booting control unit selectively cold-booting the image reproduction apparatus based on the detection of whether the error with supplying the power has occurred.

Abstract: Systems and methodologies are described that facilitate transmitting low-density parity-check encoded communications in a wireless communications network and incrementing such codes in response to requests from receiving devices. The LDPC codes can have associated constraints allowing the codes to be error corrected upon receipt. The requests for incremented codes can be in cases of low transmission power or high interference, for example, where the original code can be too error-ridden to properly decode. In this case, additional nodes can be added to current and/or subsequent communications to facilitate adding a more complex constraint to the LDPC code. In this regard, the large codes can require less validly transmitted nodes to predict error-ridden values as the additional constraint renders less ambiguity in possible node value choices.

Abstract: According to one embodiment, a memory device includes a semiconductor memory and a controller that controls the semiconductor memory. The controller includes a first command issuing module, second command issuing module, error correction module and control module. The first command issuing module is configured to issue a read command to the semiconductor memory. The second command issuing module is configured to issue a first command instructing a process that does not involve reading data from the semiconductor memory independently from the first command issuing module to the semiconductor memory. The error correction module is configured to correct an error contained in data supplied from the semiconductor memory. The control module is configured to control the error correction module, first command issuing module and second command issuing module.

Abstract: A system for predicting a failure of equipment from prior maintenance data of the equipment collected during a time duration estimate a number of preceding failures of the equipment prior to the time duration. The system constructs a model, based on the prior maintenance data, of an impact of an external intervention on a failure of the equipment. The system constructs a model, based on the constructed model of the impact of the external intervention and the estimated number of preceding failures, of a replacement policy of the equipment and a probability of a subsequent failure of the equipment in a subsequent time period.

Abstract: A redundancy system in a fault tolerant computer comprises a multiple core processor which may support a real time operating system. The multiple core machine may be actual or virtual. Multiple identical instructions, e.g., three instructions, are executed redundantly so that the redundancy system can detect and recover from a single event upset (SEU). The instructions are also displaced in time. In one form, two non-consecutive instructions are run on one core which is virtualized into two cores. Alternatively, a second actual core may provide symmetric processing. The system prevents single event functional interrupts (SEFIs) from hanging up the processor. Each core may run a separate operating system. When a first core hangs up a first operating system, the second operating system takes over operation and the processor recovers. Embedded routines may store selected data variables in memory for later recovery and perform an SEFI “self-test” routine.

Abstract: An integrated circuit 2 is provided with a data source 6 in the form of a processor executing program instructions connected via a bus interconnect 16 to a trace output device 8. The trace output device 8 is memory mapped. Different memory addresses that are mapped to the trace output device 8 are associated with different priority levels. Trace data written to at least one memory address has a first level of priority in which it is either accepted or the transfer is stalled until the data can be processed by the trace output device 8. Another level of priority associated with a different memory address is such that the data is always accepted but is discarded if the trace output device 8 does not have the ability to process, e.g. store that data at that time.