Patents Examined by Joannie A. Garcia
  • Patent number: 10068956
    Abstract: An organic light emitting display can include a substrate, a first capacitor formed on the substrate, the first capacitor including a first capacitor lower electrode, a first capacitor upper electrode, and a gate insulating layer between the first capacitor lower upper electrodes, a first passivation layer over the first capacitor, a second capacitor on the first passivation layer, the second capacitor including a second capacitor lower electrode, a second capacitor upper electrode, and a second passivation layer interposed between the second capacitor lower upper electrodes, an organic insulating layer over the second capacitor, a pixel electrode on the organic insulating layer, an organic layer on the pixel electrode, the organic layer including at least a light emitting layer, and an opposite electrode on the organic layer, and the width of the second capacitor lower electrode is greater than that of the second capacitor upper electrode.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: September 4, 2018
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Jinwoo Park
  • Patent number: 9960216
    Abstract: An organic light emitting display apparatus includes a substrate; an anode electrode on the substrate; an auxiliary electrode on the substrate; an organic emission layer on the anode electrode; a cathode electrode on the organic emission layer and on the auxiliary electrode; an insulating bank on the auxiliary electrode, the bank overlapping a first portion of the auxiliary electrode and exposing a second portion of the auxiliary electrode; a first partition wall on the auxiliary electrode; a second partition wall on the first partition wall and covering the exposed second portion of the auxiliary electrode in plan view. A separation space is between the second partition wall and the bank, the cathode electrode is electrically connected to the auxiliary electrode through the separation space between the second partition wall and the bank, and the second partition wall is supported by the first partition wall and the bank.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: May 1, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Joonsuk Lee, Se June Kim
  • Patent number: 9893315
    Abstract: A display device includes a display device including a substrate, and a display unit disposed on the substrate. An encapsulating unit encapsulates the display unit. The encapsulating unit includes a barrier organic layer. The barrier organic layer includes a plurality of organic materials and a plurality of inorganic materials. The inorganic materials are arranged in free volumes between the organic materials.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: February 13, 2018
    Assignees: SAMSUNG DISPLAY CO., LTD., INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
    Inventors: Seungyong Song, Hyojeong Kwon, Seunghun Kim, Myungmo Sung, Kwanhyuck Yoon
  • Patent number: 9887080
    Abstract: A method of forming a SiOCN material layer and a method of fabricating a semiconductor device are provided, the method of forming a SiOCN material layer including supplying a silicon source onto a substrate; supplying a carbon source onto the substrate; supplying an oxygen source onto the substrate; and supplying a nitrogen source onto the substrate, wherein the silicon source includes a non-halogen silylamine, a silane compound, or a mixture thereof.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: February 6, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kang-hun Moon, Yong-suk Tak, Gi-gwan Park
  • Patent number: 9875925
    Abstract: A method of fabricating a semiconductor device includes forming a doped polysilicon layer on a substrate, forming a barrier layer on the doped polysilicon layer, forming an oxidized barrier layer by oxidizing a surface of the barrier layer, and forming a metal layer on the oxidized barrier layer.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: January 23, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myung-ho Kong, Jeong-hee Park, Taek-jung Kim, Han-young Kim, Keon-seok Seo, Jong-myeong Lee, Hee-sook Park
  • Patent number: 9870950
    Abstract: A method of manufacturing a semiconductor device according to one or more exemplary embodiments of the present inventive concept includes forming a plurality of dummy gates on a substrate. Each of the dummy gates includes a gate mask disposed on an upper surface of each of the dummy gates. A spacer is disposed on at least two sides of the dummy gates. An insulating interlayer is formed on the gate mask and the spacer. A first polishing including chemical mechanical polishing is performed on portions of the gate mask and the insulating interlayer by using a slurry composite having a first mixing ratio. A second polishing including chemical mechanical polishing is formed on remaining portions of the gate mask and the insulating interlayer to expose upper surfaces of the plurality of dummy gates, by using a slurry composite having a second mixing ratio.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: January 16, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang-Sun Hwang, Ja-Eung Koo, Jong-Hyung Park, Ho-Young Kim, Leian Bartolome, Bo-Un Yoon, Hyoung-Bin Moon
  • Patent number: 9870940
    Abstract: Methods of forming nanosheets for a semiconductor device are provided including providing a silicon on insulator (SOI) handle wafer, the SOT handle wafer including a silicon layer and a dielectric layer on the silicon layer; providing a first donor wafer; bonding the SOI handle wafer and the first donor wafer together to provide a bonded structure; debonding the bonded structure to provide an intermediate wafer including a plurality of silicon or non-silicon nanosheets and a plurality of dielectric layers alternately stacked; and bonding the intermediate wafer to a second donor wafer to provide a final wafer including a plurality of silicon or non-silicon layers and a plurality of dielectric layers alternately stacked, wherein the final wafer includes at least one more pair of silicon or non-silicon and dielectric layers than the intermediate wafer.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: January 16, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wei-E Wang, Mark Rodder, Borna Obradovic
  • Patent number: 9842748
    Abstract: Embodiments of the present disclosure provide a liner assembly including a plurality of individually separated gas passages. The liner assembly enables tenability of flow parameters, such as velocity, density, direction and spatial location, across a substrate being processed. The processing gas across the substrate being processed may be specially tailored for individual processes with a liner assembly according to embodiment of the present disclosure.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: December 12, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Mehmet Tugrul Samir, Shu-Kwan Lau
  • Patent number: 9837629
    Abstract: An organic light emitting diode display including a substrate, a first electrode disposed on the substrate, a second electrode disposed on the substrate and separated from the first electrode, a pixel defining layer disposed on the first electrode and the second electrode, a first organic emission layer disposed on the first electrode corresponding to the first opening, a second organic emission layer disposed on the second electrode corresponding to the second opening, and a common electrode disposed on the first organic emission layer and the second organic emission layer. The first electrode includes a first dent portion. The second electrode includes a second dent portion having a different size from the first dent portion. The pixel defining layer includes a first opening exposing the first electrode corresponding to the first dent portion and a second opening exposing the second electrode corresponding to the second dent portion.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: December 5, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hae Young Yun, Jun Young Kim, Jung-Hyun Cho
  • Patent number: 9818969
    Abstract: An OLED display device includes a driving semiconductor layer on a substrate, a gate insulating layer covering the driving semiconductor layer, a driving gate electrode and etching preventing layer on the gate insulating layer, a passivation layer on the gate insulating layer, driving gate electrode, and etching preventing layer, and including a plurality of protruding and depressed patterns, driving source and drain electrodes on the passivation layer, a pixel electrode on the protruding and depressed pattern, and exposed etching preventing layer, the pixel electrode having a protruding and depressed shape, a pixel definition layer on the passivation layer, and the driving source and drain electrodes, and having a pixel opening exposing the pixel electrode, an organic emission layer on the exposed pixel electrode, and a common electrode on the organic emission layer and pixel definition layer. The protruding and depressed pattern partially exposes the etching preventing layer.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: November 14, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kyung Hoon Park, Sun Park, Chun Gi You
  • Patent number: 9812335
    Abstract: A method of fabricating a semiconductor device is disclosed. The method may include forming an target layer on a substrate, forming a mask pattern on a target layer, performing a first process to etch the target layer and form a first sub-trench, and performing a second process to further etch the target layer and form a second sub-trench. First and second sidewall patterns may be formed on a sidewall of the mask pattern to be used as an etch mask in the first and second processes, respectively. Outer sidewalls of the first and second sidewall patterns may be formed to have different angles with respect to a top surface of the substrate.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: November 7, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Je-Woo Han, Junho Yoon, Kyohyeok Kim, Dongchan Kim, Sungyeon Kim, Jaehong Park, Jinyoung Park, KyungYub Jeon
  • Patent number: 9765430
    Abstract: A plasma processing apparatus for alternately performing a first plasma processing step using first and second processing gases and a second plasma processing step using third and fourth processing gases. The apparatus includes: a processing container that has a dielectric window in a ceiling and removably accommodates a workpiece; an exhaust unit that evacuates the processing container; a processing gas supply unit that supplies the first, second, third, and fourth processing gases into the processing container; a first gas introduction unit including a top plate gas injection port, a dielectric window gas flow path, and a first external gas flow path; a second gas introduction unit including a sidewall gas injection port, a sidewall gas flow path, and a second external gas flow path; an electromagnetic wave supply unit that supplies electromagnetic waves into the plasma generating space; a bypass exhaust path; and an opening/closing valve.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: September 19, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takehisa Saito, Takenao Nemoto, Koji Yamagishi, Hiroshi Kaneko
  • Patent number: 9768412
    Abstract: A composition which can be used as an organic water/oxygen barrier material, an OLED display device and manufacturing method thereof are disclosed. The composition includes: 15-25 wt % of parylene, 15-25 wt % of polyvinyl chloride, 5-15 wt % of acetone, 5-15 wt % of trichloroethylene, 10-20 wt % of polyvinyl acetate, 5-15 wt % of polyvinyl alcohol, 0-5 wt % of SiO2 nanoparticles, and 8-12 wt % of an organic solvent, wherein all weight percent values are based on the total weight of the composition. When a water/oxygen barrier layer fabricated by the composition is disposed between a luminescent layer of OLED and a light extraction layer, water vapor and oxygen gas can be prevented from entering the OLED luminescent layer, thereby prolonging the service life of the OLED luminescent layer.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: September 19, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Haidong Wu
  • Patent number: 9711579
    Abstract: An organic light emitting diode (OLED) display includes a substrate, a thin film transistor disposed on the substrate, a first electrode disposed on the thin film transistor and electrically connected to the thin film transistor, a first auxiliary layer disposed on the first electrode, an emission layer disposed on the first auxiliary layer, an electron transport layer disposed on the emission layer, a first buffer layer disposed on the electron transport layer, and a second electrode disposed on the first buffer layer.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: July 18, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Il Soo Oh, Chang Ho Lee, Ji Hwan Yoon, Dae Yup Shin, Hee Joo Ko, Se Jin Cho, Jin Young Yun, Bora Lee, Yeon-Woo Lee, Beom Joon Kim, Pyung Eun Jeon, Hyun Ju Choi, Joong Won Sim, In Jae Lee
  • Patent number: 9685386
    Abstract: The present invention provides a semiconductor test structure for MOSFET noise testing. The semiconductor test structure includes: a MOSFET device having a first conductivity type formed on a first well region of a semiconductor substrate; a metal shielding layer formed on the MOSFET device, the metal shielding layer completely covering the MOSFET device and extending beyond the circumference of the first well region; a deep well region having a second conductivity type formed in the semiconductor substrate close to the bottom surface of the first well region, the deep well region extending beyond the circumference of the first well region; wherein a vertical via is formed between the portion of the metal shielding layer extending beyond the first well region and the portion of the deep well region extending beyond the first well region to couple the metal shielding layer to the deep well region.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: June 20, 2017
    Assignee: CSME TECHNOLOGIES FAB1 CO., LTD.
    Inventor: Xiaodong He
  • Patent number: 9670058
    Abstract: An integrated circuit includes a mechanical device for detection of spatial orientation and/or of change in orientation of the integrated circuit. The device is formed in the BEOL and includes an accommodation whose sides include metal portions formed within various metallization levels. A mobile metal component is accommodated within the accommodation. A monitor inside the accommodation defines a displacement area for the metal component and includes electrically conductive elements disposed at the periphery of the displacement area. The component is configured so as to, under the action of the gravity, come into contact with the two electrically conductive elements in response to a given spatial orientation of the integrated circuit. A detector is configured to detect an electrical link passing through the component and the electrically conductive elements.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: June 6, 2017
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Antonio Di-Giacomo, Pascal Fornara
  • Patent number: 9653630
    Abstract: The performance of lead sulfide quantum dot (QD) photovoltaic cells is improved by exposing a QD layer to a solution containing metal salts after the synthesis of the QDs is completed. The halide ions from the salt solution passivate surface lead (Pb) sites and alkali metal ions mend Pb vacancies. Metal cations and halide anions with small ionic radius have high probability of reaching QD surfaces to eliminate surface recombination sites. Compared to control devices fabricated using only a ligand exchange procedure without salt exposure, devices with metal salt treatment show increases in both the form factor and short circuit current of the PV cell. Some embodiments comprise a method for treatment of QDs with a salt solution and ligand exchange. Other embodiments comprise a photovoltaic cell having a QD layer treated with a salt solution and ligand exchange.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: May 16, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Su Kyung Suh, Dong-Kyun Ko, Vladmir Bulovic, Moungi Bawendi
  • Patent number: 9624575
    Abstract: A thin film deposition apparatus, a deposition method using the same, and a method of manufacturing an organic light-emitting display apparatus by using the apparatus are provided. A thin film deposition apparatus is provided that includes a chamber containing a substrate holder on which a substrate is mounted, a plurality of rotary shaft units that change rotation and an inclination angle of the substrate holder, and a target unit that supplies a thin film material for formation on the substrate.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: April 18, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ung-Soo Lee, Jin-Woo Park, Su-Hyuk Choi
  • Patent number: 9620414
    Abstract: A die has a first surface, a second surface opposite the first surface, and sidewalls includes a first portion and a second portion, wherein the first portion is closer to the first surface than the second portion. A fillet contacts the first portion of sidewalls of the die and encircles the die. A work piece is bonded to the die through solder bumps, with the second surface facing the work piece. A first underfill is filled a gap between the die and the work piece, wherein the first underfill contacts the fillet, and wherein the first underfill and the fillet are formed of different materials.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: April 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Yian-Liang Kuo, Ming-Song Sheu, Yu-Ling Tsai, Chen-Shien Chen, Han-Ping Pu
  • Patent number: 9607852
    Abstract: Target pattern layouts that include lower and upper target patterns are designed. Each lower target pattern is combined with a upper target pattern that at least partially overlaps a top surface thereof to form combination structures. The combination structures are divided into first and second combination structures. A first target pattern is formed from the lower target pattern in the first combination structure and a third target pattern is formed from the upper target pattern in the first combination structure. The first and third target patterns are formed in first and third lithography processes, respectively. A second target pattern is formed from the lower target pattern in the second combination structure and a fourth target pattern is formed from the upper target pattern in the second combination structure. The second and fourth target patterns are formed in second and fourth lithography processes, respectively.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: March 28, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeong-Hoon Lee, Sang-Wook Seo, Hye-Soo Shin