Patents Examined by Joannie A. Garcia
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Patent number: 9601649Abstract: A method for producing a micro system, said method comprising: providing a substrate (2) made of aluminum oxide; producing a thin film (6) on the substrate (2) by depositing lead zirconate titanate onto the substrate (2) with a thermal deposition method such that the lead zirconate titanate in the thin film (6) is self-polarized and is present predominantly in the rhombohedral phase; and cooling down the substrate (2) together with the thin film (6).Type: GrantFiled: December 11, 2014Date of Patent: March 21, 2017Assignee: PYREOS LTD.Inventors: Carsten Giebeler, Matthias Schreiter, Thorsten Steinkopff, Wolfram Wersing
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Patent number: 9583332Abstract: Implementations described herein generally relate to methods for dielectric gap-fill. In one implementation, a method of depositing a silicon oxide layer on a substrate is provided. The method comprises introducing a cyclic organic siloxane precursor and an aliphatic organic siloxane precursor into a deposition chamber, reacting the cyclic organic siloxane precursor and the aliphatic organic siloxane precursor with atomic oxygen to form the silicon oxide layer on a substrate positioned in the deposition chamber, wherein the substrate is maintained at a temperature between about 0° C. and about 200° C. as the silicon oxide layer is formed, wherein the silicon oxide layer is initially flowable following deposition, and wherein a ratio of a flow rate of the cyclic organic siloxane precursor to a flow rate of the aliphatic organic siloxane precursor is at least 2:1 and curing the deposited silicon oxide layer.Type: GrantFiled: January 6, 2015Date of Patent: February 28, 2017Assignee: APPLIED MATERIALS, INC.Inventors: Pramit Manna, Kiran V. Thadani, Abhijit Basu Mallick
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Patent number: 9583528Abstract: A MOS solid-state imaging device is provided in which withstand voltage and 1/f noise of a MOS transistor are improved. In the MOS solid-state imaging device whose unit pixel has at least a photoelectric converting portion and a plurality of field effect transistors, the thickness of gate insulating film in a part of the field effect transistors is different from the thickness of gate insulating film in the other field effect transistors among the plurality of the field effect transistors.Type: GrantFiled: October 27, 2015Date of Patent: February 28, 2017Assignee: SONY CORPORATIONInventors: Noriko Takagi, Hiroyuki Mori
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Patent number: 9583673Abstract: A semiconductor light emitting device including: a substrate made of GaAs; and a semiconductor layer formed on the substrate, in which part of the substrate on a side opposite to the semiconductor layer is removed by etching so that the semiconductor light emitting device has a thickness of not more than 60 ?m.Type: GrantFiled: November 16, 2015Date of Patent: February 28, 2017Assignee: ROHM CO., LTD.Inventors: Tadahiro Hosomi, Kentaro Mineshita
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Patent number: 9553002Abstract: Embodiments of the present disclosure provide a liner assembly including a plurality of individually separated gas passages. The liner assembly enables tenability of flow parameters, such as velocity, density, direction and spatial location, across a substrate being processed. The processing gas across the substrate being processed may be specially tailored for individual processes with a liner assembly according to embodiment of the present disclosure.Type: GrantFiled: April 23, 2014Date of Patent: January 24, 2017Assignee: APPLIED MATERIALS, INC.Inventors: Mehmet Tugrul Samir, Shu-Kwan Lau
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Patent number: 9449824Abstract: A method for an improved doping process allows for improved control of doping concentrations on a substrate. The method may comprise printing a polymeric material on a substrate in a desired pattern; and depositing a barrier layer on the substrate with a liquid phase deposition process, wherein a pattern of the barrier layer is defined by the polymeric material. The method further comprises removing the polymeric material, and doping the substrate. The barrier layer substantially prevents or reduces doping of the substrate to allow patterned doping regions to be formed on the substrate. The method can be repeated to allow additional doping regions to be formed on the substrate.Type: GrantFiled: April 24, 2014Date of Patent: September 20, 2016Assignee: Natcore Technology, Inc.Inventors: David H. Levy, Daniele Margadonna, Dennis Flood, Wendy G. Ahearn, Richard W. Topel, Jr., Theodore Zubil
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Patent number: 9449866Abstract: The invention discloses a treatment process for a semiconductor, comprising providing a substrate, the substrate comprises silicon material; defining a trench region; removing the trench region using a plasma etching process and exposing a trench surface, the trench surface comprising surface defects; forming an oxidation layer overlaying the trench surface; removing the oxidation layer and at least a portion of the surface defects; expositing a treated trench surface, the treated trench surface being substantially free from surface defects; and forming a layer of silicon germanium material overlaying the treated trench surface. The invention further provides a semiconductor processing technique used to eliminate or reduce dislocation defect on the semiconductor device and improve device performance. In the treatment process, a substrate is subjected to at least one oxidation-deoxidation processes, where an oxidation layer is formed and then removed.Type: GrantFiled: January 6, 2015Date of Patent: September 20, 2016Assignee: SHANGHAI HUALI MICROELECTRONICS CORPORATIONInventors: Quanbo Li, Jun Huang, Xiangguo Meng, Yu Zhang
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Patent number: 9442229Abstract: A method for making a hollow-structure metal grating is provided. The method includes the following steps. First, a substrate is provided. Second, a metal layer is located on a surface of the substrate. Third, a patterned mask layer is formed on a surface of the metal layer. The patterned mask layer is made of a chemical amplified photoresist. Fourth, the surface of the metal layer exposed out of the patterned mask layer is plasma etched. Lastly, the patterned mask layer on the surface of the metal layer is dissolved.Type: GrantFiled: April 28, 2014Date of Patent: September 13, 2016Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Zhen-Dong Zhu, Qun-Qing Li, Ben-Feng Bai, Shou-Shan Fan
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Patent number: 9419223Abstract: An organic light-emitting display device is provided. The organic light-emitting display device includes a plurality of first electrodes, wherein each first electrode corresponds to a sub-pixel. The display device also includes a pixel-defining layer comprising a plurality of first openings exposing at least a portion of the first electrodes, and a plurality of inlets disposed on an upper surface of the pixel-defining layer. The display device further includes an intermediate layer disposed on the exposed portion of the first electrodes and the inlets, and an opposite electrode disposed on the intermediate layer and the pixel-defining layer, wherein the inlets are selectively disposed between adjacent sub-pixels emitting light of a same wavelength.Type: GrantFiled: December 4, 2013Date of Patent: August 16, 2016Assignee: SAMSUNG DISPLAY CO., LTD.Inventor: Yoon-Ho Kang
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Patent number: 9419037Abstract: Provided is an imaging apparatus having a plurality of light receiving parts for each one microlens in order for capturing a three-dimensional image, while being capable of obtaining a more natural image when creating a two-dimensional image. The imaging apparatus includes: a microlens array (2) having a plurality of microlenses (20) regularly aligned two-dimensionally; an imaging lens for imaging light from a subject onto the microlens array (2); and a plurality of light receiving parts (22L, 22R) disposed for each of the plurality of microlenses (20). The plurality of light receiving parts (22L, 22R) associated with each microlens (20) receive the light from the subject that has been imaged onto the microlens and subject the light to photoelectric conversion. The imaging lens has a pupil which is disposed as being out of conjugation with a light receiving plane of the light receiving parts (22L, 22R).Type: GrantFiled: March 2, 2016Date of Patent: August 16, 2016Assignee: Olympus CorporationInventor: Kazuaki Murayama
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Patent number: 9412870Abstract: A device includes a substrate and a recess in the substrate. The recess has a bottom and sidewalls. The device also includes a first epitaxial layer over the bottom of the recess, and a second epitaxial layer over the first epitaxial layer and over the sidewalls of the recess, the second epitaxial layer having a different lattice constant than the substrate. The device further includes a third epitaxial layer over the second epitaxial layer and filling the recess.Type: GrantFiled: August 24, 2015Date of Patent: August 9, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: King-Yuen Wong, Chia-Yu Lu, Chien-Chang Su, Yen-Chun Lin, Yi-Fang Pai, Da-Wen Lin
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Patent number: 9391143Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.Type: GrantFiled: December 2, 2015Date of Patent: July 12, 2016Assignee: ZIPTRONIX, INC.Inventors: Qin-Yi Tong, Gaius Gillman Fountain, Jr., Paul M. Enquist
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Patent number: 9391124Abstract: An organic light emitting diode (OLED) display includes a substrate, a thin film transistor disposed on the substrate, a first electrode disposed on the thin film transistor and electrically connected to the thin film transistor, a first auxiliary layer disposed on the first electrode, an emission layer disposed on the first auxiliary layer, an electron transport layer disposed on the emission layer, a first buffer layer disposed on the electron transport layer, and a second electrode disposed on the first buffer layer.Type: GrantFiled: June 26, 2014Date of Patent: July 12, 2016Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Il Soo Oh, Chang Ho Lee, Ji Hwan Yoon, Dae Yup Shin, Hee Joo Ko, Se Jin Cho, Jin Young Yun, Bora Lee, Yeon-Woo Lee, Beom Joon Kim, Pyung Eun Jeon, Hyun Ju Choi, Joong Won Sim, In Jae Lee
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Patent number: 9379347Abstract: An organic electroluminescence element includes at least one intermediate metal layer and at least two light emitting units between an anode and a cathode. The intermediate metal layer is located between the two light emitting units. Further, the intermediate metal layer is made of a metal with a work function of 3.0 eV or lower, and has a thickness of 0.6 to 5 nm.Type: GrantFiled: July 26, 2013Date of Patent: June 28, 2016Assignee: Konica Minolta, Inc.Inventor: Tomoyuki Nakayama
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Patent number: 9349602Abstract: A semiconductor wafer spinning chuck includes a rotatable base, a plurality of arms, upstanding from the base, a selectively releasable clamping mechanism, associated with the arms, and a spray nozzle, extending through the base. The clamping mechanism has a first portion configured to mechanically clamp an edge of a first semiconductor wafer and hold the first wafer in a substantially horizontal orientation upon all of the arms, with a backside of the first wafer facing down. The spray nozzle is oriented to direct a spray of fluid at the backside of the first wafer.Type: GrantFiled: April 24, 2014Date of Patent: May 24, 2016Assignee: JST MANUFACTURING, INC.Inventors: Jacob Stafford, David Campion, Travis Deleve, Jason Boyd
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Patent number: 9343429Abstract: A semiconductor device is made by creating a gap between semiconductor die on a wafer. An insulating material is deposited in the gap. A first portion of the insulating material is removed from a first side of the semiconductor wafer to form a first notch. The first notch is less than a thickness of the semiconductor die. A conductive material is deposited into the first notch to form a first portion of the conductive via within the gap. A second portion of the insulating material is removed from a second side of the semiconductor wafer to form a second notch. The second notch extends through the insulating material to the first notch. A conductive material is deposited into the second notch to form a second portion of the conductive via within the gap. The semiconductor wafer is singulated through the gap to separate the semiconductor die.Type: GrantFiled: January 6, 2010Date of Patent: May 17, 2016Assignee: STATS ChipPAC, Ltd.Inventors: Reza A. Pagaila, Byung Tai Do
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Patent number: 9331149Abstract: A method for bonding at low or room temperature includes steps of surface cleaning and activation by cleaning or etching. The method may also include removing by-products of interface polymerization to prevent a reverse polymerization reaction to allow room temperature chemical bonding of materials such as silicon, silicon nitride and SiO2. The surfaces to be bonded are polished to a high degree of smoothness and planarity. VSE may use reactive ion etching or wet etching to slightly etch the surfaces being bonded. The surface roughness and planarity are not degraded and may be enhanced by the VSE process. The etched surfaces may be rinsed in solutions such as ammonium hydroxide or ammonium fluoride to promote the formation of desired bonding species on the surfaces.Type: GrantFiled: June 29, 2015Date of Patent: May 3, 2016Assignee: ZIPTRONIX, INC.Inventors: Qin-Yi Tong, Gaius Gillman Fountain, Jr., Paul M. Enquist
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Patent number: 9312165Abstract: A group III nitride composite substrate includes a group III nitride film and a support substrate formed from a material different in chemical composition from the group III nitride film. The group III nitride film has a thickness of 10 ?m or more. A sheet resistance of a-group III-nitride-film-side main surface of the group III nitride composite substrate is 200 ?/sq or less. A method for manufacturing a group III nitride composite substrate includes the steps of bonding the group III nitride film and the support substrate to each other; and reducing the thickness of at least one of the group III nitride film and the support substrate bonded to each other. Accordingly, a group III nitride composite substrate of a low sheet resistance that is obtained with a high yield as well as a method for manufacturing the same are provided.Type: GrantFiled: December 5, 2013Date of Patent: April 12, 2016Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventors: Akihiro Hachigo, Keiji Ishibashi, Naoki Matsumoto
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Patent number: 9305957Abstract: Provided is an imaging apparatus having a plurality of light receiving parts for each one microlens in order for capturing a three-dimensional image, while being capable of obtaining a more natural image when creating a two-dimensional image. The imaging apparatus includes: a microlens array (2) having a plurality of microlenses (20) regularly aligned two-dimensionally; an imaging lens for imaging light from a subject onto the microlens array (2); and a plurality of light receiving parts (22L, 22R) disposed for each of the plurality of microlenses (20). The plurality of light receiving parts (22L, 22R) associated with each microlens (20) receive the light from the subject that has been imaged onto the microlens and subject the light to photoelectric conversion. The imaging lens has a pupil which is disposed as being out of conjugation with a light receiving plane of the light receiving parts (22L, 22R).Type: GrantFiled: October 21, 2015Date of Patent: April 5, 2016Assignee: OLYMPUS CORPORATIONInventor: Kazuaki Murayama
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Patent number: 9306020Abstract: A power module includes a semiconductor device having at least one electrode surface on each side thereof, a first conductive member connected to the electrode surface provided on one side of the semiconductor device with solder, and a second conductive member connected to the electrode surface provided on the other side of the semiconductor device with solder, with at least one of the electrode surfaces provided on the one side of the semiconductor device being double comb-shaped.Type: GrantFiled: June 28, 2012Date of Patent: April 5, 2016Assignee: Hitachi Automotive Systems, Ltd.Inventors: Shinichi Fujino, Hideto Yoshinari, Shiro Yamashita