Abstract: An organic light emitting diode (OLED) display includes a scan line, a data line, a driving voltage line, a switching transistor, a driving transistor and an OLED. The scan line is formed on a substrate to transmit a scan signal. The data line and the driving voltage line, intersecting the scan line, transmit a data signal and a driving voltage, respectively. The switching transistor, electrically coupled to the scan line and the data line, includes a switching semiconductor layer, a switching gate electrode, and a gate insulating layer having a first thickness. The driving transistor, electrically coupled to the switching drain electrode, includes a driving semiconductor layer, a driving gate electrode and a gate insulating layer having a second thickness. The OLED is electrically coupled to the driving drain electrode. The data line and the driving voltage line are formed with different layers from each other.

Abstract: An integrated semiconductor device and method for fabricating the same are provided wherein the integrated semiconductor device comprises a substrate a first stress-inducing layer, a second stress-inducing layer and an integrated circuit layer. The first stress-inducing layer covers on the substrate. The second stress-inducing layer partially covers on the first stress-inducing layer. The integrated circuit layer is bonded over the substrate.

Abstract: A method of manufacturing photo-semiconductor device that has a photoconductive semiconductor film provided with electrodes and formed on a second substrate, the semiconductor film being formed by epitaxial growth on a first semiconductor substrate different from the second substrate, the second substrate being also provided with electrodes, the electrodes of the second substrate and the electrodes of the photoconductive semiconductor film being held in contact with each other.

Abstract: A method for making a hollow-structure metal grating is provided. The method includes providing a substrate, forming a patterned mask layer on a surface of the substrate, applying a metal layer with a thickness greater than 10 nanometers on the patterned mask layer, and removing the patterned mask layer by a washing method using organic solvent. The patterned mask layer includes a plurality of first protruding structures and a plurality of first cavities arranged in intervals.

Abstract: An improvement in a method of making a semiconducting device having a hole-collecting electrode includes coating the hole-collecting electrode with a p-type transition metal oxide through a sol-gel process.

Abstract: A method for making a metal grating is provided. The method includes providing a substrate, applying a metal layer on a surface of the substrate, forming a number of protrusions spaced from each other on a surface of the metal layer, wherein each of the number of protrusions is made of two resist layer, one of the two resist layers being made of silicone oligomer, etching the surface of the metal layer exposed out of the number of protrusions using a physical etching gas and a reactive etching gas, and dissolving the number of protrusions on the surface of the metal layer.

Abstract: Systems and methods for producing nanoscale textured low reflectivity surfaces may be utilized to fabricate solar cells. A substrate may be patterned with a resist prior to an etching process that produces a nanoscale texture on the surface of the substrate. Additionally, the substrate may be subjected to a dopant diffusion process. Prior to dopant diffusion, the substrate may be optionally subjected to liquid phase deposition to deposit a material that allows for patterned doping. The order of the nanoscale texture etching and dopant diffusion may be modified as desired to produce post-nano emitters or pre-nano emitters.

Abstract: When forming field effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art which may overcome this problem. The claimed method proposes an improved fully silicided gate achieved by forming a gate structure including an additional metal layer between the metal gate layer and the gate semiconductor material. A silicidation process can then be optimized so as to form a lower metal silicide layer comprising the metal of the additional metal layer and an upper metal silicide layer forming an interface with the lower metal silicide layer.

Abstract: A warp correction apparatus includes an injection mechanism including a nozzle that performs injection treatment, an adsorption table that holds the semiconductor element substrate by adsorption at a principal surface side or a film surface side, a moving mechanism that moves the adsorption table so that the semiconductor element substrate relatively moves with respect to an injection area of an injection particle by the nozzle, an injection treatment chamber that houses the semiconductor element substrate held on the adsorption table and in the interior of which injection treatment is performed, a measurement mechanism that measures a warp of the semiconductor element substrate, and a control device that, based on a difference between a target warp amount and a warp amount measured by the measurement mechanism, performs at least either one of a setting processing of an injection treatment condition of the injection mechanism and an accept/reject determination of the semiconductor element substrate for which

Abstract: A non-volatile memory circuit includes a non-volatile memory having a first source and drain region having a non-LOCOS offset structure and a second source and drain region having a LOCOS offset structure. A pair of switch circuits are connected in parallel to the respective first and second source and drain regions for switching voltages applied to the first and second source and drain regions so that the first source and drain region serves as a drain and the second source and drain region serves as a source in a writing mode, the second source and drain region serves as a drain and the first source and drain region serves as a source in a reading mode, and equal voltages are applied to the first source and drain region and the second source and drain region in a retention mode.

Abstract: An integrated semiconductor device and method for fabricating the same are provided wherein the integrated semiconductor device comprises a substrate a first stress-inducing layer, a second stress-inducing layer and an integrated circuit layer. The first stress-inducing layer covers on the substrate. The second stress-inducing layer partially covers on the first stress-inducing layer. The integrated circuit layer is bonded over the substrate.

Abstract: A semiconductor light emitting device including: a substrate made of GaAs; and a semiconductor layer formed on the substrate, in which part of the substrate on a side opposite to the semiconductor layer is removed by etching so that the semiconductor light emitting device has a thickness of not more than 60 ?m.

Abstract: A customized shield plate field effect transistor (FET) includes a semiconductor layer, a gate dielectric, a gate electrode, and at least one customized shield plate. The shield plate includes a conductive layer overlying a portion of the gate electrode, one of the gate electrode sidewalls, and a portion of the substrate adjacent to the sidewall. The shield plate defines a customized shield plate edge at its lateral boundary. A distance between the customized shield plate edge and the sidewall of the gate electrode varies along a length of the sidewall. The customized shield plate edge may form triangular, curved, and other shaped shield plate elements. The configuration of the customized shield plate edge may reduce the area of the resulting capacitor and thereby achieve lower parasitic capacitance associated with the FET. The FET may be implemented as a lateral diffused MOS (LDMOS) transistor suitable for high power radio frequency applications.

Abstract: Embodiments of the invention disclose an array substrate and a fabrication method thereof, and a display device. The array substrate comprises a plurality of pixel units disposed on a base substrate. Each pixel unit comprises a thin-film transistor region and a display region. A thin-film transistor structure is formed in the thin-film transistor region, and an organic light-emitting diode. The organic light-emitting diode comprises a transparent first electrode, a light-emitting layer, and a second electrode for reflecting light that are sequentially formed. A transflective layer is formed in the display region. A color filter film is formed in the display region and is disposed between the second electrode of the organic light-emitting diode and the transflective layer. The second electrode of the organic light-emitting diode and the transflective layer form a microcavity structure. The color filter films in the pixel units of different colors have different thicknesses.

Abstract: In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.

Abstract: A MOS solid-state imaging device is provided in which withstand voltage and 1/f noise of a MOS transistor are improved. In the MOS solid-state imaging device whose unit pixel has at least a photoelectric converting portion and a plurality of field effect transistors, the thickness of gate insulating film in a part of the field effect transistors is different from the thickness of gate insulating film in the other field effect transistors among the plurality of the field effect transistors.

Abstract: Provided is an imaging apparatus having a plurality of light receiving parts for each one microlens in order for capturing a three-dimensional image, while being capable of obtaining a more natural image when creating a two-dimensional image. The imaging apparatus includes: a microlens array (2) having a plurality of microlenses (20) regularly aligned two-dimensionally; an imaging lens for imaging light from a subject onto the microlens array (2); and a plurality of light receiving parts (22L, 22R) disposed for each of the plurality of microlenses (20). The plurality of light receiving parts (22L, 22R) associated with each microlens (20) receive the light from the subject that has been imaged onto the microlens and subject the light to photoelectric conversion. The imaging lens has a pupil which is disposed as being out of conjugation with a light receiving plane of the light receiving parts (22L, 22R).

Abstract: The invention relates to a device for industrially producing photovoltaic concentrator modules which consist of a module frame, a lens pane comprising a plurality of Fresnel lenses, a sensor-carrier pane, and an electric line guide, said device comprising the following features: a) a carriage (30) for retaining a module frame (1) in a tension-free manner by means of clamping elements (31) on the two longitudinal sides and stop elements (37) on the two transverse sides, these clamping elements (31) being adjusted by displacing and rotating a shift rod (32), b) a device (47) for punctually applying acrylic and linearly applying silicone (48) onto the support surfaces of the module frame (1), c) one device for laying the sensor-carrier pane (3) and one for laying the lens pane (2), these panes being conveyed in a tension-free manner using special suction devices (39) and being set down with a centrally-positioned, predetermined contact pressure, d) a device for measuring the position of each pane and for positio

Abstract: Embodiments described herein generally relate to a method of fabrication of a device structure comprising Group III-V elements on a substrate. A <111> surface may be formed on a substrate and a Group III-V material may be grown from the <111> surface to form a Group III-V device structure in a trench isolated between a dielectric layer. A final critical dimension of the device structure may be trimmed to achieve a suitably sized node structure.

Abstract: A method for manufacturing an SiC semiconductor device according to the present invention includes the steps of (a) implanting an impurity into a surface layer of an SiC substrate at a concentration of 1×1020 cm?3 or higher, (b) forming a graphite film on a surface of the SiC substrate after the step (a), (c) activating the impurity by annealing the SiC substrate after the step (b), (d) removing the graphite film after the step (c), (e) oxidizing the surface of the SiC substrate to form an oxide film after the step (d), (f) removing the oxide film, and (g) measuring resistance of the SiC substrate by a four-point probe method after the step (f).