Patents Examined by Johannes Mondt
  • Patent number: 7649241
    Abstract: A semiconductor device having a variable capacitance capacitor and a method of manufacturing the same are disclosed. An example semiconductor device includes a capacitor having a bottom electrode, a dielectric layer and an upper electrode, formed on a semiconductor substrate. The example semiconductor also includes a first insulating layer formed on the semiconductor substrate to cover the capacitor, a plurality of first contact plugs formed in a plurality of first via holes of the first insulating layer, each of which is electrically connected to either the bottom electrode or the upper electrode, a first metal wiring formed on the first insulating layer and connected to the bottom electrode through the first contact plug, a second contact plug formed on the first insulating layer and connected to the upper electrode through the first contact plug, and a second insulating layer formed on the first insulating layer to cover the first metal wiring and the second contact plug.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: January 19, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Kyung Yun Jung
  • Patent number: 7642565
    Abstract: A radiation-emitting semiconductor component has a high p-type conductivity. The semiconductor body of the component includes a substrate, preferably an SiC-based substrate, on which a plurality of GaN-based layers have been formed. The active region of these layers is arranged between at least one n-conducting layer and a p-conducting layer. The p-conducting layer is grown in tensile-stressed form. The p-doping that is used is preferably Mg.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: January 5, 2010
    Assignee: Osram GmbH
    Inventors: Stefan Bader, Berthold Hahn, Volker Härle, Hans-Jürgen Lugauer
  • Patent number: 7612388
    Abstract: The power semiconductor element has an emitter region and a stop zone in front of the emitter region. The conductivities of the emitter region and of the stop zone are opposed to one another. In order to reduce not only the static but also the dynamic loss of the power semiconductor foreign atoms are used in the stop-zone. The foreign atoms have at least one energy level within the band gap of the semiconductor and at least 200 meV away from the conduction band and valence band of the semiconductor.
    Type: Grant
    Filed: January 17, 2001
    Date of Patent: November 3, 2009
    Assignee: Infineon Technologies AG
    Inventors: Josef-Georg Bauer, Heinrich Brunner, Hans-Joachim Schulze
  • Patent number: 7611912
    Abstract: An MRAM structure is disclosed in which the bottom electrode has an amorphous TaN capping layer to consistently provide smooth and dense growth for AFM, pinned, tunnel barrier, and free layers in an overlying MTJ. Unlike a conventional Ta capping layer, TaN is oxidation resistant and has high resistivity to avoid shunting of a sense current caused by redeposition of the capping layer on the sidewalls of the tunnel barrier layer. Alternatively, the ?-TaN layer is the seed layer in the MTJ. Furthermore, the seed layer may be a composite layer comprised of a NiCr, NiFe, or NiFeCr layer on the ?-TaN layer. An ?-TaN capping layer or seed layer can also be used in a TMR read head. An MTJ formed on an ?-TaN capping layer has a high MR ratio, high Vb, and a RA similar to results obtained from MTJs based on an optimized Ta capping layer.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: November 3, 2009
    Assignee: Headway Technologies, Inc.
    Inventors: Liubo Hong, Cheng Horng, Mao-Min Chen, Ru-Yin Tong
  • Patent number: 7590213
    Abstract: A system and method for storing spent nuclear fuel that affords adequate cooling capabilities under “smart flood” criteria.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: September 15, 2009
    Inventor: Krishna P. Singh
  • Patent number: 7215001
    Abstract: A semiconductor device capable of controlling an operation of a fuse element by increasing a resistance of the fuse element without fusing the fuse wiring by the laser beam irradiation comprises a semiconductor substrate, a first wiring formed above the semiconductor substrate, a second wiring formed above the first wiring, at least one plug which acts as a fuse element to connect the first wiring and the second wiring, and an opening made in a part of an insulator formed above the second wiring so as to correspond to the plug.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: May 8, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihiro Kajita
  • Patent number: 7215005
    Abstract: The invention describes the fabrication and structure of an ESD protection device for integrated circuit semiconductor devices with improved ESD protection and resiliency. A vertical bipolar npn transistor forms the basis of the protection device. To handle the large current requirements of an ESD incident, the bipolar transistor has multiple base and emitter elements formed in an npn bipolar array. To assure turn-on of the multiple elements of the array the emitter fingers are continuously or contiguously connected with an unique emitter design layout. The contiguous emitter design provides an improved electrical emitter connection for the device, minimizing any unbalance that can potentially occur when using separate emitter fingers and improving the ability for the simultaneous turn on of the multiple emitter-base elements.
    Type: Grant
    Filed: March 2, 2004
    Date of Patent: May 8, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Ta-Lee Yu
  • Patent number: 7211836
    Abstract: A high emission intensity group-III nitride semiconductor light-emitting device obtained by eliminating crystal lattice mismatch with substrate crystal and using a gallium nitride phosphide-based light emitting structure having excellent crystallinity. A gallium nitride phosphide-based multilayer light-emitting structure is formed on a substrate via a boron-phosphide (BP)-based buffer layer. The boron phosphide-based buffer layer is preferably grown at a low temperature and rendered amorphous so as to eliminate the lattice mismatch with the substrate crystal. After the amorphous buffer layer is formed, it is gradually converted into a crystalline layer to fabricate a light-emitting device while keeping the lattice match with the gallium nitride phosphide-based light-emitting part.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: May 1, 2007
    Assignee: Showa Denko Kabushiki Kaisha
    Inventor: Takashi Udagawa
  • Patent number: 7202538
    Abstract: A MOSFET transistor structure is formed in a substrate of semiconductor material having a first conductivity type. The MOSFET transistor structure includes an active region that is surrounded by a perimeter isolation dielectric material formed in the substrate to define a continuous sidewall interface between the sidewall dielectric material and the active region. Spaced-apart source and drain regions are formed in the active region and are also spaced-apart from the sidewall interface. A conductive gate electrode that is separated from the substrate channel region by intervening gate dielectric material includes a first portion that extends over the substrate channel region and a second portion that extends continuously over the entire sidewall interface between the isolation dielectric material and the active region.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: April 10, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Philipp Lindorfer, Vladislav Vashchenko, Robert Drury
  • Patent number: 7183576
    Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitakial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon <1020 cm?3, the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850° C. and rapid thermal anneal temperatures to 1000° C.
    Type: Grant
    Filed: February 10, 2004
    Date of Patent: February 27, 2007
    Assignee: International Business Machines Corporation
    Inventors: Jack Oon Chu, Basanth Jagannathan, Alfred Grill, Bernard Steele Meyerson, John Albrecht Ott
  • Patent number: 7183534
    Abstract: A photodetector includes a light emitting portion for applying light, a light receiving portion for sensing the light, and a light guiding member 3 for guiding the light from the light emitting portion to a surface to be measured and guiding detection light from the surface to be measured to the light receiving portion. The light guiding member has a sheet-like optical transmission medium, which is disposed at a portion facing to the surface to be measured and transmits the light by internal reflection. The sheet-like optical transmission member has an optical aperture facing to the surface to be measured.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: February 27, 2007
    Assignee: Fuji Xerox Co., Ltd
    Inventor: Tohru Hisano
  • Patent number: 7183611
    Abstract: The invention includes SRAM constructions comprising at least one transistor device having an active region extending into a crystalline layer comprising Si/Ge. A majority of the active region within the crystalline layer is within a single crystal of the crystalline layer, and in particular aspects an entirety of the active region within the crystalline layer is within a single crystal of the crystalline layer. The SRAM constructions can be formed in semiconductor on insulator assemblies, and such assemblies can be supported by a diverse range of substrates, including, for example, glass, semiconductor substrates, metal, insulative materials, and plastics. The invention also includes electronic systems comprising SRAM constructions.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: February 27, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 7141855
    Abstract: A dual-thickness active device layer SOI chip structure is provided. The SOI chip structure has an active device layer, at least one oxide region located at a predetermined position of the active device layer and with a first predetermined depth, at least one trench surrounding the oxide region and having a second predetermined depth greater than the first predetermined depth, and a ground layer connected to the active device layer and the oxide region. The SOI structure further has a first silicon-based wafer and a second wafer. Both wafers are bonded together by wafer bonding. At least two different active device layer thicknesses exist to meet requirements of a wide variety of SOI devices placed thereon, with the setting of the oxide region filled with thermal oxide or other oxide variations.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: November 28, 2006
    Assignee: Via Technologies, Inc.
    Inventor: Ray Chien
  • Patent number: 7087973
    Abstract: A transistor is formed with a source ballast resistor that regulates channel current. In an LDMOS transistor embodiment, the source ballast resistance may be formed using a high sheet resistance diffusion self aligned to the polysilicon gate, and/or by extending a depletion implant from under the polysilicon gate toward the source region. The teachings herein may be used to form effective ballast resistors for source and/or drain regions, and may be used in many types of transistors, including lateral and vertical transistors operating in a depletion or an enhancement mode, and BJT devices.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: August 8, 2006
    Assignee: Micrel, Incorporated
    Inventors: Shekar Mallikarjunaswamy, Martin J. Alter, Charles L. Vinn
  • Patent number: 7057238
    Abstract: A semiconductor device and a method for fabricating the same are provided. The provided semiconductor device includes a field oxide layer formed in a semiconductor substrate to define an active region; gate structures formed on the active region; source/drain junctions formed on either side of the gate structures on the semiconductor substrate; a channel silicon layer arranged under the gate insulating layer to operate as a channel for connecting sources and drains; and buried junction isolation insulating layers under the channel silicon layer. The buried junction isolation insulating layers isolate source/drain junction regions of a MOS transistor, so that a short circuit in a bulk region under the channel of a transistor due to the high-integration of the device can be prevented.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: June 6, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-young Kim, Ki-nam Kim
  • Patent number: 7045859
    Abstract: A trench type power MOSgated device has a plurality of spaced trenches lined with oxide and filled with conductive polysilicon. The tops of the polysilicon fillers are below the top silicon surface and are capped with a deposited oxide the top of which is flush with the top of the silicon. Source regions of short lateral extent extend into the trench walls to a depth below the top of the polysilicon. A trench termination is formed having an insulation oxide liner covered by a polysilicon layer, covered in turn by a deposited oxide.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: May 16, 2006
    Assignee: International Rectifier Corporation
    Inventors: Adam I. Amali, Naresh Thapar
  • Patent number: 7042020
    Abstract: A light emitting device uses a source of exciting radiation such as an light emitting diode to excite a photo luminescent material to provide a source of visible light.
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: May 9, 2006
    Assignee: Cree, Inc.
    Inventor: Gerald H. Negley
  • Patent number: 7042040
    Abstract: A semiconductor memory device comprises select transistors formed on side surfaces of plural silicon columns defined by a grid-like trenches on a surface of a silicon substrate, each select transistor having a source and a drain on the top surface and the bottom of the silicon column. A capacitor is formed on the top surface of the silicon column to form a DRAM cell. The source/drain layers on the bottom of a greater number of memory cells are commonly connected, or the source/drain layers on the bottom of adjacent memory cells are commonly connected, to be brought out to the surface of the silicon substrate by a connection line to be connected to a constant voltage or a bit line.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: May 9, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Fumio Horiguchi
  • Patent number: 7023029
    Abstract: In an ESD protection device using a SCR-like structure, a vertical device is provided that is highly robust and easily allows the triggering voltage to be adjusted during manufacture. Furthermore it is implementable in complementary form based on PNP and NPN BJT structures, to provide both positive and negative pulse protection.
    Type: Grant
    Filed: August 2, 2002
    Date of Patent: April 4, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Ann Concannon, Peter J. Hopper, Marcel ter Beek
  • Patent number: 7012313
    Abstract: A MOS transistor in a single-transistor memory cell having a locally thickened gate oxide, and a process for producing the transistor. The MOS transistor can be used as a selection transistor in a single-transistor memory cell having nitride spacers, or another spacer material acting as an oxidation barrier. The transistor also has a bird's beak in the gate oxide to reduce leakage currents. The MOS transistor can be used in a DRAM, particularly as a selection transistor.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: March 14, 2006
    Assignee: Infineon Technologies AG
    Inventors: Lars-Peter Heineck, Giorgio Schweeger