Abstract: A semiconductor package is mounted to a support plate through a base. The base is inserted between a rear face of the semiconductor package and a front face of the support plate. An electrical connection mechanism is provided to connect the semiconductor package to the support plate pass. This mechanism passes through the base. The mounting of the semiconductor package is accomplished by a variety of structures to fasten the package onto the said support plate. These structures cooperate with and are placed below the rear face of the semiconductor package.

Abstract: A thick film millimeter wave transceiver module includes a base plate and a multi-layer substrate board having a plurality of layers of low temperature transfer tape received on the base plate. The different layers can vary. They can include a DC signals layer having signal tracks in connection; a ground layer having ground connections; a device layer having capacitors and resistors embedded therein; and a top layer having cut-outs for receiving MMIC chips therein. A solder preform layer is located between the device layer and the top layer for securing any MMIC chips. A channelization plate is received over the multi-layer substrate board and a channel is formed to receive MMIC chips and provide isolation between transmit and receive signals.

Abstract: Laser diodes containing aluminum at high concentration in an active layer have been usually suffered from remarkable facet deterioration along with laser driving operation and it has been difficult for the laser diodes to attain high reliability. An aluminum oxide film lacking in oxygen is formed adjacent to the semiconductor on an optical resonator facet, by which facet deterioration can be minimized and, accordingly, the laser diode can be operated with no facet deterioration at high temperature for long time and a laser diode of high reliability can be manufactured at a reduced cost.

Abstract: An electronic semiconductor device has a sublithographic contact area between a first conductive region and a second conductive region. The first conductive region is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region has a second thin portion having a second sublithographic dimension in a second direction transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area. The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

Abstract: A plurality of transistor cells (T) are arranged in the semiconductor layer (4). Ring-shaped p-type layers (1b) and n-type layers (1a) composed of polysilicon film are formed alternately on an insulating layer (6) in an outer side than the plurality of transistor cells (T) (the peripheral portion of chip), thereby forming a protective diode (1). The most outer layer of the protective diode (1) is contacted to the gate wiring (2) composed of metal film such as Al, which is formed circularly on the most external layer, and the most inner layer is contacted to the source wiring composed of metal layer, thereby the protective diode is connected between the gate and source of a transistor. As a result of this, the semiconductor device with the protective diode which has the small series resistance, can be formed without enlarging chip area and by using unoccupied space of chip, and realize protection function sufficiently, can be obtained.

Abstract: A CMOS-compatible FET has a reduced electron affinity polycrystalline or microcrystalline SiC gate that is electrically isolated (floating) or interconnected. The SiC material composition is selected to establish the barrier energy between the SiC gate and a gate insulator. In a memory application, such as a flash EEPROM, the SiC composition is selected to establish a lower barrier energy to reduce write and erase voltages and times or accommodate the particular data charge retention time needed for the particular application. In a light detector or imaging application, the SiC composition is selected to provide sensitivity to the desired wavelength of light. Unlike conventional photodetectors, light is absorbed in the floating gate, thereby ejecting previously stored electrons therefrom. Also unlike conventional photodetectors, the light detector according to the present invention is actually more sensitive to lower energy photons as the semiconductor bandgap is increased.

Abstract: A microelectronic device including an insulator located over a substrate, a semiconductor feature and a contact layer. The semiconductor feature has a thickness over the insulator, a first surface opposite the insulator, and a sidewall spanning at least a portion of the thickness. The contact layer has a first member extending over at least a portion of the first surface and a second member spanning at least a portion of the sidewall.

Abstract: A mesa-shaped superconducting-superlattice structure is formed and adhered with epoxy onto a dielectric substrate where plural superconducting layers and plural insulating layers are naturally and alternately stacked. A ?/4 micro strip line (which means the length of the strip line is one-fourth of the wavelength of a microwave to be introduced) is electrically connected via a metallic film onto the mesa structural portion of the superconducting-superlattice structure, and a metallic electrode is electrically connected to the additional mesa structural portion of the superconducting-superlattice structure via a metallic film.

Abstract: A pixel having a structure in which low voltage drive is possible is provided by a simple process. A digital image signal input from a source signal line is input to the pixel through a switching TFT. At this point, a voltage compensation circuit amplifies the voltage amplitude of the digital image signal or transforms the amplitude, and applies the result to a gate electrode of a driver TFT. On-off control of TFTs within the pixel can thus be performed normally even if the voltage of a power source for driving gate signal lines becomes lower.

Abstract: Provided is an organic thin film transistor comprising a polymeric layer interposed between a gate dielectric and an organic semiconductor layer. Various homopolymers, copolymers, and functional copolymers are taught for use in the polymeric layer. An integrated circuit comprising a multiplicity of thin film transistors and methods of making a thin film transistor are also provided. The organic thin film transistors of the invention typically exhibit improvement in one or more transistor properties.

Abstract: A semiconductor laser device, module, and method for providing light suitable for providing an excitation light source for a Raman amplifier. The semiconductor laser device includes an active layer configured to radiate light, a spacer layer in contact with the active layer and a diffraction grating formed within the spacer layer, and configured to emit a light beam having a plurality of longitudinal modes within a predetermined spectral width of an oscillation wavelength spectrum of the semiconductor device. A plurality of longitudinal modes within a predetermined spectral width of an oscillation wavelength spectrum is provided by changing a wavelength interval between the longitudinal modes and/or widening the predetermined spectral width of the oscillation wavelength spectrum.

Abstract: A semiconductor light emitting element comprising: a first layer; a semiconductor light emitting layer; a current blocking layer; a second layer; a first electrode; and a second electrode is provided. The semiconductor light emitting layer is selectively provided on the first layer. The current blocking layer of high resistance is provided around the semiconductor light emitting layer on the first layer. The second layer is provided on the semiconductor light emitting layer and the current blocking layer. The first electrode is provided on the second layer. The second electrode is provided on the back of the first layer. A part of a light emitted from the semiconductor light emitting layer is emitted outside through the first layer, and a part of the light emitted from the semiconductor light emitting layer is emitted outside through the second layer.

Abstract: According to one embodiment, a timing circuit (300) can include a first control circuit (302), a first clocked circuit (304), a second clocked circuit (306), and a second control circuit (314). A first control circuit (302) may compensate for a first timing signal FCLK making a transition earlier in time than a second timing signal RCLK. A second control circuit (314) may compensate for a second timing signal RCLK making a transition earlier in time than a first timing signal FCLK. A first timing signal FCLK can be a periodic signal generated by a first PLL type circuit (310) in response to a falling edge of an external clock signal EXT CLK. A second timing signal RCLK can be a periodic signal generated by a second PLL type circuit (312) in response to a rising edge of an external clock signal EXT CLK.

Abstract: A method of forming a corrugated capacitor on a semiconductor component. The method of forming the corrugated capacitor comprises a series of depositing alternating layers of doped silicon glass having different etch rates on a semiconductor component, covering the alternating layers with an etch-resistant material, and etching the alternating layers, thereby forming a capacitor structure having corrugated sides.

Abstract: A thin film transistor substrate and a fabricating method thereof that are capable of improving an aperture ratio. A gate electrode on that substrate has an inclined head and a concave neck.

Abstract: A semiconductor device has a first semiconductor element and a second semiconductor element formed on a semiconductor substrate. The second semiconductor element is operated with a first voltage. The first semiconductor element is operated with a second voltage that is higher than the first voltage. The pairs of impurity regions of the first and second semiconductor elements respectively have first impurity areas and second impurity areas. Each of the first impurity areas have a predetermined impurity concentration and a conductivity type opposite to a conductivity type of the semiconductor substrate. The second impurity areas extend toward their corresponding gates from the first impurity areas. The second impurity areas have a same conductivity type as the first impurity areas and an impurity concentration lower than the concentration of the first impurity area.

Abstract: A semiconductor laser device is constructed by stacking a buffer layer, an undoped GaN layer, an n-GaN contact layer, an n-InGaN crack preventing layer, an n-AlGaN cladding layer, a light emitting layer, a p-AlGaN cladding layer, and a p-GaN contact layer in this order. A ridge portion comprising the p-GaN contact layer and the p-AlGaN cladding layer is formed, and the thickness of the p-AlGaN cladding layer in the ridge portion is less than 0.3 ?m.

Abstract: To propose a new channel structure suitable for high efficiency source side injection, and provide a non-volatile semiconductor memory device and a charge injection method using the same. The non-volatile memory device includes a first conductivity type semiconductor substrate (SUB), a first conductivity type inversion layer-forming region (CH1), second conductivity type accumulation layer-forming regions (ACLa, ACL2b), second conductivity type regions (S/D1, S/D2), an insulating film (GD0) and a first conductive layer (CL) formed on the inversion layer-forming region (CH1). A charge accumulation film (GD) and a second conductive layer (WL) are stacked on an upper surface and side surface of the first conductive layer (CL), an exposure surface of the inversion layer-forming region (CH1), and an upper surface of the accumulation layer-forming regions (ACLa, ACLb) and the second conductivity type regions (S/D1, S/D2).

Abstract: A photovoltaic device including a plurality of unit devices stacked, each unit device comprising a silicon-based non-single-crystal semiconductor material and having a pn or pin structure, in which an oxygen atom concentration and/or a carbon atom concentration has a maximum peak in the vicinity of a p/n interface between the plurality of unit devices.

Abstract: A process and structure for forming electrical devices. The process and structure provide for forming an insulating layer on a substrate. A conductive region is then formed in the insulating layer by implanting silicon atoms into the insulating layer. Further, a plurality of different conductive regions can be formed in the insulating layer. An electrical device such as a transistor or a diode can then be formed in each of the conductive regions. Because the conductive regions are formed in a conductive region which is largely electrically isolated from other conductive regions there is little possibility for adjacent devices to cause interference.