Abstract: In the present invention, a semiconductor device is formed which includes an MIM capacitor located on the upper surface of a heterostructure from which the emitter, base and collector sections of a nearby HBT are defined. In this way the capacitor and HBT share a substantially common structure, with the base and emitter electrodes of the HBT fashioned from the same metal layers as the upper and lower capacitor plates, respectively. Furthermore, as the insulator region of the capacitor is formed prior to definition of the HBT structure, the dielectric material used can be deposited by means of a plasma enhanced process, without damaging the HBT structure.

Abstract: A transistor device includes a gate region disposed adjacent to a semiconductor substrate such that a low impedance channel is formed between a source region and drain region of a transistor device when a voltage is applied to its gate. The drain region of the device can be disposed aside the gate region on a common surface of the semiconductor substrate. The source region of the device also can be disposed adjacent to the substrate but on a side of the semiconductor substrate opposing the drain and/or gate regions. Based on this topology, a transistor device can be fabricated with a buried source to enhance its operating characteristics such as switching speed.

Abstract: A semiconductor device including an electrostatic protection circuit capable of preventing current from being concentrated in a hot spot through a silicide layer. A plurality of salicide N-type MOS transistors isolated by a first diffusion region are formed on a semiconductor substrate of this semiconductor device. An NPN lateral bipolar transistor and a Zener diode are formed as an electrostatic protection circuit for these MOS transistors. The NPN lateral bipolar transistor includes a P-type well and a second diffusion region which is formed in a region isolated by two second isolation regions. The Zener diode is formed by the PN junction between the first diffusion region of the MOS transistor and a third diffusion region. The breakdown start voltage of the Zener diode is set to be lower than the breakdown start voltage of the MOS transistor.

Abstract: A vertically structured semiconductor power component is described. A layer thickness of a substrate of the power module between a pn junction and a metallized back is chosen in such a manner that a space charge region produced in the semiconductor component extends as far as the back when a blocking voltage between a source and a drain electrode is applied before a field strength produced by the applied blocking voltage reaches a critical value.

Abstract: A group III nitride compound semiconductor light-emitting element of a flip chip bonding type for emitting light with a wavelength not longer than 400 nm is coupled to a Zener diode, and the light-emitting element and the Zener diode coupled to each other are sealed with a metal casing having a window.

Abstract: An integrated structure formed on a semiconductor chip includes a substrate having a first conductivity type and an epitaxial layer grown on the substrate. The epitaxial layer may have the first conductivity type and also a conductivity less than a conductivity of the substrate. Moreover, the integrated structure may include a first region and a second region in the epitaxial layer, each having a conductivity type opposite that of the epitaxial layer. The first and second regions may extend from a surface of the epitaxial layer opposite the substrate into the epitaxial layer to form respective first and second junctions therewith. Further, the integrated structure may also include an isolating element for reducing an injection of current through the epitaxial layer from the first region to the second region when the first junction is directly biased.

Abstract: A method for fabricating a capacitor of a semiconductor device, and a capacitor made in accordance with the method, wherein the method includes forming a plate electrode polysilicon layer on a semiconductor substrate having a cell array region and a core/peripheral circuit region. The plate electrode polysilicon layer in the cell array region is patterned to form an opening, wherein the inner wall of the opening is used as a plate electrode. After forming a dielectric layer in the opening, a storage node is formed as a spacer on the dielectric layer on the inner wall of the opening. The plate electrode polysilicon layer in the core/peripheral circuit region remains to provide the same height between the cell array region where the cell capacitor is formed and the core/peripheral circuit region.

Abstract: An active matrix substrate comprises a substrate, a position control member provided on the substrate and surrounding a specific space by a sidewall thereof to expose a surface of the substrate and whose inner side face inclines at a specific angle with respect to the substrate, an active element provided so as to engage with the inner side face of the position control member and whose outer side face has at least a part that inclines at substantially the same angle as the specific angle of the inner side face of the position control member with respect to the substrate, and an adhesion section which bonds the active element to the substrate or the position control member and whose wettability with the position control member is lower than that of the adhesive with the substrate.

Abstract: A transverse JFET of SiC, employing an n-type SiC substrate and comprising a channel region having carriers of high mobility, bringing a high yield is obtained. This transverse JFET comprises an n-type SiC substrate (1n), a p-type SiC film (2) formed on the right face of the n-type SiC substrate, an n-type SiC film (3), including a channel region (11), formed on the p-type SiC film, source and drain regions (22, 23) formed on the n-type SiC film separately on both sides of the channel region respectively, and a gate electrode (14) provided in contact with the n-type SiC substrate (1n).

Abstract: A non-volatile semiconductor memory device having a memory cell array region in which a plurality of memory cells, each having first and second MONOS memory cells controlled by a word gate and control gates, are arranged in first and second directions. The memory cell array region has a plurality of sector regions divided in the second direction. Each of a plurality of control gate drivers is capable of setting a potential of first and second control gates in the corresponding sector region independently of other sector regions. A plurality of switching elements which select connection/disconnection are formed at connections between a plurality of main bit lines and a plurality of sub bit lines.

Abstract: A method and apparatus for testing semiconductors comprising stacked floating gate structures. A floating gate is programmed (710). An electrical stress or disturb voltage is applied to a control gate with a source and a drain in a specific set of conditions (720). Subsequent to the stressing, a drain current versus gate voltage relationship is measured (730). The sequence of programming, stressing and measuring may be repeated (740) with different conditions for source and drain. More particularly, positive and negative biases are applied to a source while a drain is held at ground, and similar biases are applied to a drain while a source is held at ground. Through inspection of the measurement information taken after this sequence of stress applications, a stack gate edge-defect may be identified (750) as associated with a source edge or a drain edge.

Abstract: The field emission type electron source device of the present invention includes: a field emission electron source portion including an extraction electrode provided on a p-type silicon substrate via an insulating film and having an opening portion at a position corresponding to a region where a cathode is provided; and a cathode portion provided on the p-type silicon substrate and at a position corresponding to the opening portion of the extraction portion; and an n-channel field effect transistor portion provided on the p-type silicon substrate, corresponding to the field emission electron source portion. The field emission electron source portion is provided in a drain region of the field effect transistor portion. A control voltage is applied to a gate electrode of the field effect transistor portion to control a field emission current from the field emission electron source portion. The drain region includes at least two wells having different impurity concentrations.

Abstract: Structures and methods for preventing fluorine diffusion from a fluorinated dielectric material having a low dielectric constant are disclosed. Various fluorine diffusion barriers are described, each of which comprises doped or undoped silicon in combination with tantalum, tantalum nitride, tantalum silicide, cobalt, cobalt silicide, or mixtures thereof. Fluorine diffusion from fluorinated dielectrics is stopped by the barriers at temperatures as high as 450° C. In practice, one of the disclosed fluorine diffusion barriers is positioned between a fluorine-containing insulator and a conductive metal interconnect or metal interconnect diffusion barrier, thereby preventing diffusion of the fluorine atoms into the adjacent interconnect/barrier.

Abstract: A level shifter is provided that facilitates reducing high-bias-voltage application to a MOSFET and improving the reliability thereof. The level shifter includes an NMOSFET formed of a first isolated region in the surface portion of a P-type substrate, a source, a channel and a drain in the surface portion of a first isolated region, and a gate above the first isolated region; a second isolated region in the surface portion of P-type substrate and space apart from first isolated region; and high-potential portions including pinch resistance with a high breakdown voltage in second isolated region.

Abstract: A photodiode comprises an optical detection portion for detecting an optical signal and outputting a photoelectric conversion signal. The optical detection portion has a semiconductor substrate of a first conductive type and semiconductor layers of a second conductive type formed in spaced-apart relation in a surface of the semiconductor subtrate. A depletion layer is formed in the semiconductor subtrate by application of a reverse bias to the photodiode so as to surround the semiconductor layers. An etched surface portion of the depletion layer is disposed between the semiconductor layers so that an interface level region of the surface of the semiconductor substrate does not exist between the semiconductor layers.

Abstract: A method for manufacturing a power transistor circuit includes securing a die to a substrate, the die comprising a transistor having an input terminal and an output terminal. One or more performance characteristics of the transistor are measured. Using one or more wire sets, the transistor input terminal is electrically connected to one or more input matching elements and an input signal lead. The impedance of the one or more wire sets, as determined by selecting a desired number and/or length of the wires in each set, is selected based at least in part on the measured transistor performance characteristic(s). Similarly, using one or more additional wire sets, the transistor output terminal is electrically connected to one or more output matching elements and an output signal lead, wherein the impedance of the additional wire sets is selected based at least in part on the measured transistor performance characteristic(s).

Abstract: A power semiconductor device having a low on-resistance and a high breakdown ruggedness is disclosed. Trench regions formed so as to contact trench gates via gate-insulating films are connected by emitter regions so as to form a ladder-shaped configuration. The emitter regions are formed at a shallower depth than the trench regions. Therefore, the resistance in portions of the body that are near the interfaces with the emitter regions is reduced, and the operation of parasitic transistors formed by the emitter regions, the body, and an epitaxial layer is substantially prevented. As a result, the on-resistance is varied, and the avalanche ruggedness and the latch-up ruggedness are improved.

Abstract: A semiconductor laser stack apparatus 1 comprises three semiconductor lasers 2a to 2c, two copper plates 3a and 3b, two lead plates 4a and 4b, a supply tube 5, a discharge tube 6, four insulating members 7a to 7d, and three heat sinks 10a to 10c. Here, the heat sink 10a to 10c is formed by a lower planar member 12 having an upper face formed with a supply water path groove portion 22, an intermediate planar member 14 formed with a plurality of water guiding holes 38, and an upper planar member 16 having a lower face formed with a discharge water path groove portion 30 which are successively stacked one upon another, whereas their contact surfaces are joined together.

Abstract: A memory device includes a data layer having a magnetization that can be oriented in first and second directions; and a synthetic ferrimagnet reference layer. The data and reference layers have different coercivities.

Abstract: An n− type layer 12 is epitaxially grown on one main surface (front surface) of an n+ type silicon substrate 11 and an anode electrode 13 is electrically in contact with the other main surface (rear surface) thereof. A p type region 14 is selectively formed in a surface layer of the n− type layer 12 and a n+ type region 15 is selectively formed in a surface layer of the p type region 14. A cathode electrode 17 is electrically in contact with a surface of the n+ type region 15.