Abstract: A method of forming a memory cell includes forming a first polysilicon block over an upper surface of a semiconductor substrate and having top surface and a side surface meeting at a sharp edge, forming an oxide layer with a first portion over the upper surface, a second portion directly on the side surface, and a third portion directly on the sharp edge, performing an etch that thins the oxide layer in a non-uniform manner such that the third portion is thinner than the first and second portions, performing an oxide deposition that thickens the first, second and third portions of the oxide layer, wherein after the oxide deposition, the third portion is thinner than the first and second portions, and forming a second polysilicon block having one portion directly on the first portion of the oxide layer and another portion directly on the third portion of the oxide layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first semiconductor layer, an insulating layer and a second semiconductor layer in a substrate. The method also includes forming a first isolation feature in the first semiconductor layer, the insulating layer and the second semiconductor layer. The method further includes forming a transistor in and over the substrate adjacent to the first isolation feature. In addition, the method includes etching the first isolation feature to form a trench extending below the insulating layer. The method also includes filling the trench with a metal material to form a second isolation feature in the first isolation feature.

Abstract: Disclosed is a device that includes a crystalline substrate and a patterned aluminum-based material layer disposed onto the crystalline substrate. The patterned aluminum-based material layer has a titanium-alloyed surface. A titanium-based material layer is disposed over select portions of the titanium-alloyed surface. In an exemplary embodiment, the patterned aluminum-based material layer forms a pair of interdigitated transducers to provide a surface wave acoustic (SAW) device. The SAW device of the present disclosure is usable to realize SAW-based filters for wireless communication equipment.

Abstract: A vacuum channel field effect transistor includes a first insulator on a p-type semiconductor substrate, a gate electrode on the first insulator, a second insulator on the gate electrode, a drain electrode on the second insulator, and an n+ impurity diffusion layer in the surface of the p-type semiconductor substrate, the n+ impurity diffusion layer being in contact with a side wall including side faces of the first insulator, the gate electrode, and the second insulator. Application of predetermined voltages to the n+ impurity diffusion layer, the gate electrode, and the drain electrode causes charge carriers in the n+ impurity diffusion layer to travel through a vacuum or air faced by the side wall to the drain electrode, which can increase the source-drain current.

Abstract: Provided are various three-dimensional flash memory devices. A three-dimensional flash memory device includes a gate stacked structure, separate arc-shaped channel pillars, source/drain pillars and a charge storage structure. The gate stacked structure is disposed on a substrate and includes a plurality of gate layers electrically insulated from each other. The arc-shaped channel pillar are disposed on the substrate and located in the gate stacked structure. The source/drain pillars are disposed on the substrate and penetrate through the gate stacked structure, wherein two source/drain pillars are disposed at two ends of each of the arc-shaped channel pillars. The charge storage structure is disposed between each of the plurality of gate layers and the corresponding arc-shaped channel pillar.

Abstract: A method for depositing an oxide film on a substrate by a cyclical deposition is disclosed. The method may include: depositing a metal oxide film over the substrate utilizing at least one deposition cycle of a first sub-cycle of the cyclical deposition process; and depositing a silicon oxide film directly on the metal oxide film utilizing at least one deposition cycle of a second sub-cycle of the cyclical deposition process. Semiconductor device structures including an oxide film deposited by the methods of the disclosure are also disclosed.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.

Abstract: A nonvolatile memory device is provided. The nonvolatile memory device comprises a floating gate arranged over a first active region, whereby the first active region is in an active layer of a substrate. A metal-insulator-metal (MIM) capacitor may be provided laterally adjacent to the floating gate, whereby a portion of the metal-insulator-metal capacitor is in the active layer. A contact pillar may connect a first electrode of the metal-insulator-metal capacitor to the floating gate.

Abstract: Fan-out panel level packages (FOPLPs) comprising warpage control structures and techniques of formation are described. An FOPLP may comprise one or more redistribution layers; a semiconductor die on the one or more redistribution layers; one or more warpage control structures adjacently located next to the semiconductor die; and a mold compound encapsulating the semiconductor die and the one or more warpage control structures on the one or more redistribution layers. The FOPLP can be coupled a board (e.g., a printed circuit board, etc.). The warpage control structures can assist with minimizing or eliminating unwanted warpage, which can occur during or after formation of an FOPLP or a packaged system. In this way, the warpage control structures can assist with reducing costs associated with semiconductor packaging and/or manufacturing of an FOPLP or a packaged system.

Abstract: Methods of cutting gate structures, and structures formed, are described. In an embodiment, a structure includes first and second gate structures over an active area, and a gate cut-fill structure. The first and second gate structures extend parallel. The active area includes a source/drain region disposed laterally between the first and second gate structures. The gate cut-fill structure has first and second primary portions and an intermediate portion. The first and second primary portions abut the first and second gate structures, respectively. The intermediate portion extends laterally between the first and second primary portions. First and second widths of the first and second primary portions along longitudinal midlines of the first and second gate structures, respectively, are each greater than a third width of the intermediate portion midway between the first and second gate structures and parallel to the longitudinal midline of the first gate structure.

Abstract: The application discloses a method of applying the stress memorization technique in making the semiconductor device which includes: step 1: forming a front gate structure on a silicon wafer having front and back surfaces; step 2: forming sidewalls including a first silicon nitride sidewall, a first silicon nitride layer corresponding to the first silicon nitride sidewall covering a first polysilicon layer on the wafer's back surface; step 3: growing a second silicon nitride layer on the wafer's front surface; step 4: etching the silicon nitride after stress transfer is completed, including: step 41: performing front single-wafer wet etching; step 42: performing batch wet etching to completely remove the second silicon nitride layer and reduces the thickness of the first silicon nitride layer on the back surface; step 5: completing the subsequent process. The application can improve the wafer flatness for improved photolithography for back-end-of-line processes and thereby increasing product yield.

Abstract: Disclosed herein are magnetic structures in integrated circuit (IC) package supports, as well as related methods and devices. For example, in some embodiments, an IC package support may include a conductive line and a magnetic structure around a top surface of the conductive line and side surfaces of the conductive line. The magnetic structure may have a tapered shape that narrows toward the conductive line.

Abstract: A substrate processing method includes providing a substrate containing a first semiconductor material and a second semiconductor material, treating the first semiconductor material and the second semiconductor material with a chemical source that selectively forms a chemical layer on the second semiconductor material relative to the first semiconductor material, and exposing the substrate to a first metal-containing precursor that selectively deposits a first metal-containing layer on the first semiconductor material relative to the chemical layer on the second semiconductor material.

Abstract: According to one embodiment, a semiconductor memory device includes: a stacked structure including a plurality of first layers stacked with a second layer therebetween above a substrate having a memory region in which a plurality of memory cells are arranged and an outer edge portion surrounding the memory region, the stacked structure having a stepped portion at which ends of the first layers form a stepped shape at an end of the stacked structure in a first direction within the memory region, wherein at least some of the first layers among the plurality of first layers extend, along a second direction perpendicular to the first direction, from above the outer edge portion at a first end side of the substrate through above the memory region over the substrate to above the outer edge portion at a second end side of the substrate.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon. A plurality of gate structures is over the fin, individual ones of the plurality of gate structures along a direction orthogonal to the fin and having a pair of dielectric sidewall spacers. A trench contact structure is over the fin and directly between the dielectric sidewalls spacers of a first pair of the plurality of gate structures. A contact plug is over the fin and directly between the dielectric sidewalls spacers of a second pair of the plurality of gate structures, the contact plug comprising a lower dielectric material and an upper hardmask material.

Abstract: According to an embodiment, a semiconductor memory device includes a semiconductor substrate, a control circuit arranged on the semiconductor substrate, and a memory cell array arranged above the control circuit. The memory cell array includes a plurality of three-dimensionally-arranged memory cells, and is controlled by the control circuit. A first nitride layer is arranged between the control circuit and the memory cell array, and a second nitride layer is arranged between the control circuit and the first nitride layer.

Abstract: A high-electron mobility transistor includes a substrate layer, a first buffer layer provided on the substrate layer, a barrier layer provided on the first buffer layer, a source provided on the barrier layer, a drain provided on the barrier layer, and a gate provided on the barrier layer. The transistor further includes a p-type material layer having a length parallel to a surface of the substrate layer over which the first buffer layer is provided, the length of the p-type material layer being less than an entire length of the substrate layer. The p-type material layer is provided in one of the following: the substrate layer, or the first buffer layer. A process of making the high-electron mobility transistor is disclosed as well.

Abstract: A semiconductor device includes a stacked structure with insulating layers and conductive layers that are alternately stacked on each other, a hard mask pattern located on the stacked structure, a channel structure penetrating the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure, and a memory layer interposed between the stacked structure and the channel structure, wherein the memory layer fills a space between the insulating patterns, wherein a sidewall of each of the conductive layers protrudes farther towards the channel structure than a sidewall of the hard mask pattern, and wherein the insulating patterns protrude farther towards the channel structure than the sidewall of each of the conductive layers.

Abstract: A memory cell includes: a first electrode; a resistive material layer comprising one horizontal portion and two vertical portions that are respectively coupled to ends of the horizontal portion; and a second electrode, wherein the second electrode is partially surrounded by a top boundary of the U-shaped profile and the first electrode extends along part of a bottom boundary of the U-shaped profile.

Abstract: According to one embodiment, a semiconductor device includes an element region, an element isolation region adjacent to the element region, a gate insulating layer provided on an upper surface of the element region, and a gate electrode including a semiconductor layer, the semiconductor layer containing boron (B) and including a portion provided on the gate insulating layer, the element isolation region including an upper portion including an upper surface of the element isolation region and a lower portion including a lower surface of the element isolation region, and the upper portion of the element isolation region applying compressive stress to a portion of the element region, which is adjacent to the upper portion of the element isolation region.