Patents Examined by John A Bodnar
  • Patent number: 11264342
    Abstract: Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: March 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Ming-Da Cheng, Mirng-Ji Lii, Meng-Tse Chen, Wei-Hung Lin
  • Patent number: 11257732
    Abstract: A semiconductor module includes: a semiconductor element; a first lead frame including a first portion on which the semiconductor element is mounted; a sealing member sealing the semiconductor element and the first portion; and a heat dissipation member which is integrated with the sealing member and dissipates heat generated in the semiconductor element. The heat dissipation member is insulated from the semiconductor element and the first portion by the sealing member. Therefore, the semiconductor module that is applicable to vertical semiconductor elements and ensures electrical insulation between the semiconductor element and the heat dissipation member when implementing the semiconductor module onto a circuit board, can be provided.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: February 22, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Maki Hasegawa, Shuhei Yokoyama, Shogo Shibata, Shigeru Mori, Toru Iwagami
  • Patent number: 11254563
    Abstract: Embodiments include a microelectronic device package structure having a die on a substrate, where a first side of the die is electrically coupled to the substrate, and a second side of the die is covered with a first material having a first thermal conductivity. A second material is adjacent to a sidewall of the die and adjacent to a sidewall of the first material. The second material has second thermal conductivity, smaller than the first thermal conductivity. The second material may have mechanical and/or underfill properties superior to those of the first material. Together, the two materials may provide a package structure having enhanced thermal and mechanical performance.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: February 22, 2022
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Nitin A. Deshpande
  • Patent number: 11251094
    Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having an oxygen vacancy passivating bottom spacer. In a non-limiting embodiment of the invention, a first semiconductor fin is formed in a first region of a substrate and a second semiconductor fin is formed in a second region of the substrate. A bilayer bottom spacer is formed in direct contact with sidewalls of the semiconductor fins. The bilayer bottom spacer includes a first layer and an oxygen-donating second layer positioned on the first layer. A first dielectric film is formed on the sidewalls of the first semiconductor fin. The first dielectric film terminates on the first layer. A second dielectric film is formed on the sidewalls of the second semiconductor fin. The second dielectric film extends onto a surface of the oxygen-donating second layer.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: February 15, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Choonghyun Lee, Takashi Ando, Alexander Reznicek, Jingyun Zhang
  • Patent number: 11251181
    Abstract: Embodiments of the disclosure provide a semiconductor device including a substrate, an insulating layer formed over the substrate, a plurality of fins formed vertically from a surface of the substrate, the fins extending through the insulating layer and above a top surface of the insulating layer, a gate structure formed over a portion of fins and over the top surface of the insulating layer, a source/drain structure disposed adjacent to opposing sides of the gate structure, the source/drain structure contacting the fin, a dielectric layer formed over the insulating layer, a first contact trench extending a first depth through the dielectric layer to expose the source/drain structure, the first contact trench containing an electrical conductive material, and a second contact trench extending a second depth into the dielectric layer, the second contact trench containing the electrical conductive material, and the second depth is greater than the first depth.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: February 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Che Tsai, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
  • Patent number: 11251034
    Abstract: There is provided a film forming method comprising an organic substance removal step of removing an organic substance adhering to an oxide film generated on a surface of a base by supplying a hydrogen-containing gas and an oxygen-containing gas to the base; an oxide film removal step of removing the oxide film formed on the surface of the base after the organic substance removal step; and a film forming step of forming a predetermined film on the surface of the base after the oxide film removal step.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: February 15, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiroyuki Hayashi, Rui Kanemura, Satoshi Takagi, Mitsuhiro Okada
  • Patent number: 11244869
    Abstract: A method of forming a logic device and a power device on a substrate is provided. The method includes forming a first vertical fin on a first region of the substrate and a second vertical fin on a second region of the substrate, wherein an isolation region separates the first region from the second region, forming a dielectric under-layer segment on the second vertical fin on the second region, and forming a first gate structure on the dielectric under-layer segment and second vertical fin on the second region.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: February 8, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juntao Li, Kangguo Cheng, Liying Jiang, John G. Gaudiello
  • Patent number: 11239086
    Abstract: Embodiments described herein relate to substrate processing methods. More specifically, embodiments of the disclosure provide for an MRAM back end of the line integration process which utilizes a zero mark for improved patterning alignment. In one embodiment, the method includes fabricating a substrate having at least a bottom contact and a via extending from the bottom contact in a first region and etching a zero mark in the substrate in a second region apart from the first region. The method also includes depositing a touch layer over the substrate in the first region and the second region, depositing a memory stack over the touch layer in the first region and the second region, and depositing a hardmask over the memory stack layer in the first region and the second region.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: February 1, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Hsin-wei Tseng, Mahendra Pakala, Lin Xue, Jaesoo Ahn, Sajjad Amin Hassan
  • Patent number: 11239419
    Abstract: The present invention relates to a structure of a memory device. The structure of a memory device includes a substrate, including a bottom electrode layer formed therein. A buffer layer is disposed on the substrate, in contact with the bottom electrode layer. A resistive layer surrounds a whole sidewall of the buffer layer, and extends upward vertically from the substrate. A mask layer is disposed on the buffer layer and the resistive layer. A noble metal layer is over the substrate, and fully covers the resistive layer and the mask layer. A top electrode layer is disposed on the noble metal layer.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: February 1, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hai Tao Liu, Li Li Ding, Yao-Hung Liu, Guoan Du, Qi Lu Li, Chunlei Wan, Yi Yu Lin, Yuchao Chen, Huakai Li, Hung-Yueh Chen
  • Patent number: 11227797
    Abstract: Embodiments described herein relate to methods of seam-free gapfilling and seam healing that can be carried out using a chamber operable to maintain a supra-atmospheric pressure (e.g., a pressure greater than atmospheric pressure). One embodiment includes positioning a substrate having one or more features formed in a surface of the substrate in a process chamber and exposing the one or more features of the substrate to at least one precursor at a pressure of about 1 bar or greater. Another embodiment includes positioning a substrate having one or more features formed in a surface of the substrate in a process chamber. Each of the one or more features has seams of a material. The seams of the material are exposed to at least one precursor at a pressure of about 1 bar or greater.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: January 18, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Shishi Jiang, Kurtis Leschkies, Pramit Manna, Abhijit Mallick
  • Patent number: 11193843
    Abstract: Aspects of the disclosure provide a capacitive pressure sensor. The capacitive pressure sensor can include a first substrate having a first surface and a second surface, a movable plate at a bottom of a first cavity recessed into the substrate from the first surface, and a second substrate bonded to the first substrate over the first surface. A second cavity is formed between the movable plate and the second surface. The second substrate includes a fixed plate disposed over the movable plate to form a capacitor. The second substrate further includes a third cavity between a surface of the fixed plate opposite to the movable plate and a surface of the second substrate opposite to the first substrate.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: December 7, 2021
    Inventors: Kathirgamasundaram Sooriakumar, Anu Austin, Ian Rose Bihag, Dieter Naegele-Preissmann
  • Patent number: 11177247
    Abstract: A display apparatus includes a driving substrate and a first light emitting diode element. The driving substrate has a plurality of driving structures. Each of the driving structures includes a first pad, a second pad, a third pad and a fourth pad. The plurality of driving structures include a first driving structure. The first light emitting diode element is electrically connected to a first pad and a second pad of the first driving structure, and the first light emitting diode element crosses a line connecting a third pad and a fourth pad of the first driving structure. A manufacturing method of the display apparatus is also provided.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: November 16, 2021
    Assignee: Au Optronics Corporation
    Inventor: Chung-Chan Liu
  • Patent number: 11164996
    Abstract: A method of manufacturing a semiconductor light-emitting device includes: preparing a layer stack including a light-extracting layer and a light-emitting structure, the light-extracting layer having a first principal surface and a second principal surface opposite to the first principal surface, the light-emitting structure being provided on the first principal surface of the light-extracting layer; forming a pattern mask over a partial region of the second principal surface; dry-etching the second principal surface to form a rugged structure in a region where the pattern mask is formed and to form a recess portion having a planar surface in a region that is exposed without having the pattern mask formed thereover; and singulating the layer stack by irradiating the planar surface with a laser and cutting at least the light-extracting layer at a position of the planar surface.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: November 2, 2021
    Assignee: NIKKISO CO., LTD.
    Inventors: Noritaka Niwa, Tetsuhiko Inazu
  • Patent number: 11158714
    Abstract: Disclosed herein are quantum dot devices with trenched substrates, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate having a trench disposed therein, wherein a bottom of the trench is provided by a first material, and a quantum well stack at least partially disposed in the trench. A material of the quantum well stack may be in contact with the bottom of the trench, and the material of the quantum well stack may be different from the first material.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: October 26, 2021
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Van H. Le, Jeanette M. Roberts, David J. Michalak, James S. Clarke, Zachary R. Yoscovits
  • Patent number: 11152397
    Abstract: A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, and a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the first oxide semiconductor layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: October 19, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Tomoya Futamura, Takahiro Kasahara
  • Patent number: 11145597
    Abstract: A semiconductor device includes a first semiconductor chip on which a first circuit is formed and a second semiconductor chip on which two circuits are formed. In the first semiconductor chip, a first inductor on the transmitting side electrically connected with the first circuit and a second inductor on the receiving side electrically connected with the second circuit via the bonding wire are formed. In plan view, the first inductor and the second inductor are disposed so as not to overlap each other, and are arranged along each other.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: October 12, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Kuwabara, Yasutaka Nakashiba, Teruhiro Kuwajima
  • Patent number: 11139295
    Abstract: A FinFET device structure is provided. The FinFET device structure includes an isolation structure formed over a substrate and a fin structure formed over the substrate. The FinFET device structure includes a first gate structure and a second gate structure formed over the fin structure, and the first gate structure has a first width in a direction parallel to the fin structure, the second gate structure has a second width in a direction parallel to the fin structure, and the first width is smaller than the second width. The first gate structure includes a first work function layer having a first height. The second gate structure includes a second work function layer having a second height and a gap between the first height and the second height is in a range from about 1 nm to about 6 nm.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: October 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chai-Wei Chang, Po-Chi Wu, Yi-Cheng Chao, Che-Cheng Chang
  • Patent number: 11133232
    Abstract: A semiconductor device is provided. The semiconductor device includes a functional circuit; a plurality of electrostatic discharge (ESD) protection circuits formed independently of the functional circuit, wherein each of the plurality of ESD protection circuits includes a plurality of junctions having different sizes and capacities, each of the plurality of ESD protection circuits is configured to perform an ESD test in different processes of fabrication of the semiconductor device; and a plurality of test pads connected to the plurality of ESD protection circuits and the functional circuit, respectively, wherein each of the plurality of test pads is configured to receive a test signal for the ESD test.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: September 28, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ae-Nee Jang, Seung-Duk Baek
  • Patent number: 11127674
    Abstract: Disclosed are embodiments of a back end of the line (BEOL) metal structure that includes, within a metal level, a metal via, which has at least eight sides and all interior angles at 135° or more, and a metal wire thereon. The metal wire and via include respective portions of a continuous conformal metal layer. A passivation layer coats the top surface of the metal layer. The metal via and the metal wire thereon can be in an upper metal level and can be made of one metal (e.g., aluminum or an aluminum alloy). The upper metal level can be above a lower metal level that similarly includes a metal via and metal wire thereon, but the metal used can be different (e.g., copper) and/or the shape of the via can be different (e.g., four-sided). Also disclosed herein are method embodiments for forming the above-described BEOL metal structure.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: September 21, 2021
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Dirk Breuer, Oliver M. Witnik, Carla Byloos, Holger S. Schuehrer
  • Patent number: 11127730
    Abstract: A semiconductor device including memory cell transistors on a substrate is provided. The semiconductor device includes a first wiring layer on the memory cell transistors and including a bit line and a first conductive pattern, a second wiring layer on the first wiring layer and including a ground line, a first via interposed between and electrically connecting the bit line and a source/drain of a first memory cell transistor among the memory cell transistors, and a first extended via interposed between the ground line and a source/drain of a second memory cell transistor among the memory cell transistors. The ground line is electrically connected to the source/drain of the second memory cell transistor through the first extended via and the first conductive pattern. The first extended via has a width greater than that of the first via.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: September 21, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Inhak Lee, Sang-Yeop Baeck, JaeSeung Choi, Hyunsu Choi, SangShin Han