Abstract: A system and method for automatically generating a control bifurcation signal to configure ports of a PCIe IO unit on a computing device. The lanes of the PCIe IO unit are divided into initial ports of the lowest granularity. It is determined whether a PCIe device is connected to each of the initial ports. The bifurcation port configuration of the PCIe IO unit is determined based on the initial ports having a connected PCIe device. Ports for the PCIe IO unit are configured based on the bifurcation port configuration.

Abstract: A remote technical support system includes an edge device that operates as a highly secured conduit for a technician to view, access, and control a target device via a secure protocol over a connection medium between the edge device and the target device. The edge device's architecture allows it to selectively present numerous peripheral devices to the target device. The architectural components of the edge device can be controlled by a technician through a secure connection with a trusted server which allows authorized to access the edge device. The edge device also relays technician commands to and obtains diagnostic information from the target device and communicates feedback to the technician over the secure connection. The commands may be relayed to the target via the one or more selectively connected USB peripherals.

Abstract: A method for operating a control unit, in particular for a motor vehicle, the control unit including at least one execution unit for executing task programs, a first task program and a second task program being executed at least intermittently, the first task program providing data for the second task program at the end of a first predefined time interval, wherein a transfer of the data from the first task program to the second task program only takes place after a particular last execution of the first task program within a predefined second time interval for the execution of the second task program, the second time interval being longer than the first time interval.

Abstract: A system and method for automatically generating a control bifurcation signal to configure ports of a PCIe IO unit on a computing device. The lanes of the PCIe IO unit are divided into initial ports of the lowest granularity. It is determined whether a PCIe device is connected to each of the initial ports. The bifurcation port configuration of the PCIe IO unit is determined based on the initial ports having a connected PCIe device. Ports for the PCIe IO unit are configured based on the bifurcation port configuration.

Abstract: A wireless docking system has a host (100) and at least one dockee (120,130,140). The host accommodates at least one wireless docking environment including at least one peripheral (110,111,112). The host has a host communication unit (102) for providing wireless communication and a host processor (101) arranged for docking the dockee into the wireless docking environment. The dockee has a dockee communication unit (121) for providing said wireless communication, and a dockee processor (122) arranged for docking into the wireless docking environment. The dockee has at least one dockee peripheral (123). The dockee processor advertises the dockee peripheral, and, upon receiving a coupling request from the host, couples to the host for providing connection data and control of the dockee peripheral by the host. The host processor advertises the set of peripherals including the dockee peripheral for making the dockee peripheral available for use as a further peripheral in the wireless docking environment.

Abstract: In an aspect of the disclosure, an apparatus, a computer-readable medium, and a method are provided. The apparatus may be a service processor. The service processor receives, a first command or data of a UBM protocol from a UBM host running on a host of the service processor. The UBM protocol is a first protocol supported by the service processor. The first command or data instructs a backplane controller of the host to perform a first task. The service processor generates a second command or data of a second protocol supported by the service processor. The second command or data instructs the backplane controller to perform the first task. The service processor sends the second command or data to the backplane controller.

Abstract: A solid state drive having a drive aggregator and multiple component solid state drives. Different component solid state drives in solid state drive are configured with different optimizations of memory/storage operations. An address map in the solid state drive is used by the drive aggregator to host different namespaces in the component solid state drives based on optimization requirements of the namespaces and based on the optimizations of memory operations that have been implement in the component solid state drives.

Abstract: An apparatus to is provided, to be used with an interconnect comprising a home node. The apparatus includes general-purpose storage circuitry and specialised storage circuitry. Transfer circuitry performs a non-forwardable transfer of a data item from the general-purpose storage circuitry to the specialised storage circuitry. Transmit circuitry transmits an offer to the home node, at a time of the non-forwardable transfer, to transfer the data item to the home node. The apparatus is inhibited from forwarding the data item from the specialised storage circuitry to the home node.

Abstract: Provided are a mobile terminal-based NFC stress testing method and system, and a storage device. The method comprises: connecting to a computer to acquire a preset count and a preset frequency; activating an NFC service; determining whether a flag bit is enabled, and if so, detecting an NDEF message, or if not, waiting for the computer terminal to modify the flag bit to be enabled before detecting an NDEF message; and uploading, by a hardware abstraction layer, the NDEF message to an NFC application, disabling a service flag bit, and returning to wait for the computer terminal to modify the flag bit, until detection is complete.

Abstract: A device for communicating with a slave device includes a communication module; a memory; and at least one processor configured to control the communication module and the memory, wherein the memory stores instructions configured, when the device operates, for the at least one processor to acquire a device identifier (ID) of the slave device, acquire a first data transmission rate for data communication with the slave device based on the acquired device ID and a first time period corresponding to a current time, and communicate with the slave device based on the acquired first data transmission rate, and the first data transmission rate acquired by the processor is substantially the same as a first data transmission rate calculated by the slave device based on the first time period.

Abstract: A memory module includes a plurality of memory integrated circuit (IC) packages to store data and a command buffer IC to buffer one or more memory commands destined for the memory IC packages. The command buffer IC includes a first interface circuit and one or more second interface circuits. The first interface circuit receives the one or more memory commands. The one or more second interface circuits output a pre-programmed command sequence to one or more devices separate from the command buffer IC, the pre-programmed command sequence output in response to the one or more memory commands matching a pre-programmed reference command pattern.

Abstract: An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU performs operations for signaling an interrupt to the guest operating system. For these operations, the IOMMU acquires, from an entry in an interrupt remapping table associated with the guest operating system, a location in a virtual advanced programmable interrupt controller (APIC) backing page for the guest operating system in the guest portion of the memory. The IOMMU then writes information about the interrupt to the location in the virtual APIC backing page. The IOMMU next communicates an indication of the interrupt to the guest operating system.

Abstract: Disclosed is a method for detecting an erroneous bus node address allocation in data bus systems with auto addressing using an addressing current, such as LIN data bus systems with auto addressing. The method comprises performing auto addressing of the n bus nodes, causing an addressing current to be supplied by a bus node, sensing the data bus current by the bus nodes and determining a bus node-specific bus current measurement value, deciding, whether an addressing current flows through the respective bus node, and determining a bus node-specific addressing current presence value, transmitting the bus node-specific bus current measurement value and/or the bus node-specific addressing current presence value from the bus node to the bus master, forming a supply bus node-specific result vector from the received bus node-specific addressing current presence values, and comparing the supply bus node-specific result vector and a supply bus node-specific expectation vector.

Abstract: According to one general aspect, a device may include a host interface circuit configured to communicate with a host device via a data protocol that employs data messages. The device may include a storage element configured to store data in response to a data message. The host interface circuit may be configured to detect when a tunneling command is embedded within the data message; extract a tunneled message address information from the data message; retrieve, via the tunneled message address information, a tunneled message stored in a memory of the host device; and route the tunneled message to an on-board processor and/or data processing logic. The on-board processor and/or data processing logic may be configured to execute one or more instructions in response to the tunneled message.

Abstract: Access to a memory shared between a first interface and a second interface is arbitrated. Following a request to access the memory emanating from the second interface, while current access to the memory is granted to the first interface, a count is triggered having a maximum count time. A access to the memory is authorized for the second interface at the end of occupation of the access granted to the first interface if the end of occupation finishes before the end of the maximum count time, or otherwise at the end of the maximum count time.

Abstract: State machine engines are disclosed, including those having an inter-rank bus control system, which may include a register. The state machine engine may include a plurality of configurable elements, such that each of the plurality of configurable elements comprises a plurality of memory cells. These cells may analyze data and output a result of the analysis. The IR bus control system may halt a write operation of data to be analyzed by the cells based, at least in part, on one or more conditions.

Abstract: Systems and methods are described for modifying input and output (I/O) to an object storage service by implementing one or more owner-specified functions to I/O requests. A function can implement a data manipulation, such as filtering out sensitive data before reading or writing the data. The functions can be applied prior to implementing a request method (e.g., GET or PUT) specified within the I/O request, such that the data to which the method is applied may not match the object specified within the request. For example, a user may request to obtain (e.g., GET) a data set. The data set may be passed to a function that filters sensitive data to the data set, and the GET request method may then be applied to the output of the function. In this manner, owners of objects on an object storage service are provided with greater control of objects stored or retrieved from the service.

Abstract: An information flow control device has: a first network interface card on a transmission side, the first network interface card including first and second transceivers, each of the first and second transceivers having a transmit port and a receive port; and a second network interface card on a receiving side, the second network interface card including at least one receive port. A first data connection segment connects the first transceiver transmit port to the second transceiver receive port, a second data connection segment connects the second transceiver transmit port to the first transceiver receive port, and a third data connection segment connects the first transceiver transmit port to the receive port of the second network interface card. The first and second segments provide continuity, while the third segment provides one-way data transfer. The first and second transceivers are replaceable with third and fourth transceivers to provide different throughput.

Abstract: Apparatuses, systems, and methods for hierarchical memory systems are described. A hierarchical memory system can leverage persistent memory to store data that is generally stored in a non-persistent memory, thereby increasing an amount of storage space allocated to a computing system at a lower cost than approaches that rely solely on non-persistent memory. An example method includes receiving an interrupt message by a hypervisor, the interrupt message generated by a hierarchical memory component responsive to receiving a read request initiated by an input/output (I/O) device, gathering, by the hypervisor, address register access information from the hierarchical memory component, and determining, by the hypervisor, a physical location of data associated with the read request.

Abstract: A system on chip includes an interconnect circuit including at least p input interfaces and at least k output interfaces, p source devices respectively coupled to the p input interfaces and k access ports respectively coupled to the k output interfaces and belonging to a target that includes one or more target devices. Each source device is configured to deliver transactions to the target via one of the access ports. An associated memory of each access port is configured to temporarily store the transactions received by the access port. The target is configured to deliver, for each access port, a fill signal representative of a current fill level of its associated memory. A control circuit is configured to receive the fill signals from the access ports and select the access ports eligible to receive a transaction depending on the current fill levels.