Abstract: A peripheral device of a computing device may include a processor; a sharing module to, upon execution of the processor, allow the peripheral device to be shared with an external computing device over a network; and a communication module to, upon execution of the processor: provide data from the peripheral device to a peripheral device hub module of a computing device; and provide communication by the peripheral device with the external computing device.

Abstract: A controller area network bus based security communications system includes a gateway electronic control unit (ECU) and at least one control area network (CAN) bus ECU. The gateway ECU generates a random number, and sends the random number to the at least one CAN bus ECU. A first CAN bus ECU obtains the random number sent by the gateway ECU, and generates a first information authentication code based on a key of a first CAN identifier, the random number sent by the gateway ECU, a count value of the first CAN identifier, and data of a first CAN packet.

Abstract: An interrupt handler unit (130) generates a timer interrupt at an interrupt time, and executes an interrupt preparation process. A wait time period measurement unit (142) a measures a time period from completion of the interrupt preparation process to generation of a start request (201) as a wait time period. A time calculation unit (441) calculates a subtraction time period based on the wait time period measured by the wait time period measurement unit (142), and calculates a preparation time period that is the sum of a time period obtained by subtracting the subtraction time period from the wait time period and a processing time period of the interrupt preparation process. The time calculation unit (441) stores a time obtained by shifting back the preparation time period from the time of a next start request (201), as a next interrupt time, in a time storage unit (442).

Abstract: An interrupt signal is provided to a guest operating system. A bus connected module is operationally connected with a plurality of processors via a bus attachment device. The bus attachment device receives an interrupt signal from the bus connected module with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is running using a running indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor is running, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.

Abstract: A method and electronic device are disclosed herein. The electronic device includes at least one connector, at least one switch electrically connected to the at least one connector, a sensor, a memory, and a processor electrically connected to the at least one connector, the at least one switch, the sensor, and the memory. The processor implements the method, including detecting insertion of an external device into the at least one connector based on an electrical signal input through the at least one connector, receiving biometric information using the sensor after detecting the insertion of the external device, and controlling a switch electrically connected to the connector to be connected to the connector into which the external device is inserted when the received biometric information matches biometric information stored in the memory.

Abstract: This disclosure provides a method and apparatus for saving and restoring state information of a wireless device with varying amounts of available power, such as wireless devices that may harvest power from radio-frequency signals. The wireless device may save and restore varying amounts of state information based at least in part on the amount of power available. In some embodiments, some of the stored state information may be lost as the available power decreases.

Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.

Abstract: Intelligent connection systems disclosed herein perform autonomous connection mechanisms and provide secure connectors. A mobile device exemplifies one of the embodiments of the autonomous connection mechanism.

Abstract: An apparatus to facilitate source synchronous signaling is disclosed. The apparatus includes transfer protocol logic to provide for source synchronous transfer of data within an interconnect fabric, including one or more synchronizers having logic to a transmit data signal and a source clock (clk) signal during the transfer of data.

Abstract: Systems, apparatuses, and methods related to hierarchical memory are described herein. A hierarchical memory apparatus can be part of a memory system that can leverage persistent memory to store data that is generally stored in a non-persistent memory. An example apparatus includes logic circuitry configured to receive a command indicating that an access to a base address register coupled to the logic circuitry has occurred. The command can be indicative of a data access involving a persistent memory device and/or a non-persistent memory device. The logic circuitry can determine that the access command corresponds to an operation to divert data from the non-persistent memory device to the persistent memory device, generate an interrupt signal, and cause the interrupt signal to be asserted on a host coupleable to the logic circuitry as part of the operation to divert data from the non-persistent memory device to the persistent memory device.

Abstract: Techniques are disclosed for a hybrid undo/redo for text editing, where non-linear undo and redo operations are performed across dynamic regions in a document and linear undo and redo operations are performed within the dynamic regions in the document. In an example, the hybrid undo/redo may be achieved by maintaining respective region offset values for the dynamic regions created in a document by the edits made to the document. In operation, the respective region offset values associated with the dynamic regions can be used to negate or otherwise counteract the effect of edits made in the dynamic regions.

Abstract: Embodiments determine anomalies in sensor data generated by a plurality of sensors that correspond to a single asset. Embodiments receive a first time window of clean sensor input data generated by the sensors, the clean sensor data including anomaly free data comprised of clean data points. Embodiments divide the clean data points into training data points and evaluation data points, and divide the training data points into a pre-defined number of plurality of segments of equal length. Embodiments convert each of the plurality of segments into corresponding segment curves using Kernel Density Estimation (“KDE”) and determine a Jensen-Shannon (“JS”) divergence value for each of the plurality of segments using the segment curves to generate a plurality of JS divergence values. Embodiments then assign the maximum value of the plurality of JS divergence values as a threshold value and validate the threshold value using the evaluation data points.

Abstract: A data storage system includes a storage medium including plurality of memory cells, a storage controller in communication with the storage medium, an electrical interface circuitry configured to pass data via a channel disposed between the storage medium and the storage controller; and voltage training circuitry configured to train a high-level output voltage (VOH) for each of a plurality of data lines of the channel. Training the VOH includes, for each of the plurality of data lines of the channel, calibrating a pull-up driver of the storage controller against an on-die termination circuit of the storage medium, calibrating a pull-down driver of the storage controller against the pull-up driver of the storage controller, and calibrating an on-die termination circuit of the storage controller against a pull-up driver of the storage medium.

Abstract: Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width reduction based on the instantaneous throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamic bus module to configure a bus width for a client of the interconnect fabric based on throughput demand from the client.

Abstract: A data storage system can transfer user-generated data from a data storage device to a host responsive to a host workload that consists of data read requests from the host received at a requested rate. A completion rate of a data read request can be delayed in accordance to a data access uniformity strategy to nominally match the requested rate.

Abstract: One example method includes receiving an IO request from an application, determining if an affinity policy applies to the application that transmitted the IO request, when an affinity policy applies to the application, directing the IO request to a specified site of a replication system, when no affinity policy applies to the application, determining if a lag in replication of the IO request from a primary site to a replication site is acceptable, if a lag in replication of the IO request is acceptable, processing the IO request using performance based parameters and/or load balancing parameters, and if a lag in replication of the IO request is not acceptable, either directing the IO request to a most up to date replica site, or requesting a clone copy of a volume to which the IO request was initially directed and directing the IO request to the cloned copy.

Abstract: The present disclosure relates to a method of scheduling messages to be exchanged between tiles in a computer where there is a fixed transmission time between sending and receiving tiles. According to the method a total size of message data to be sent or received by each tile is determined. One of the tiles is selected based at least on the size of the message data to schedule a first message. The first message to be scheduled is selected from the set of messages on that tile. In order to schedule the message the other end points of this selected message are determined, and then respective time slots are allocated at the sending and receiving tiles for that message. The size of the selected message is then deducted from each of the tiles acting as end points for the message, and then the sequence is carried out again until all messages have been scheduled. This technique optimises message exchange in an exchange phase of a BSP system.

Abstract: A method and system configured to receive a first report from a computer peripheral device by a receiver, determine that the first report is corrupted or received at a rate slower than the first report rate, compute a current trajectory of the computer peripheral device based on one or more intervals of movement data in the first report, compute a predicted trajectory of the computer peripheral device based on the first report, compute an incremental displacement of the computer peripheral device based on the predicted trajectory. The method and system can further generate data indicative of a position or displacement of the computer peripheral device based on the predicted trajectory of the computer peripheral device and send the data indicative of a position or displacement of the computer peripheral device at an interval that is less than twice a period of the first report rate to the host computing device.

Abstract: A port descriptor of a selected port descriptor version is obtained. The selected port descriptor version is one port descriptor version of a plurality of port descriptor versions available for selection. The port descriptor of the selected port descriptor version includes information relating to a port of the computing environment and is configured to include technology information indicating whether the port is part of a multiple lane connector packaging. A determination is made using the port descriptor of one or more operational attributes of the port. Action is taken based on the one or more operational attributes of the port.

Abstract: A port descriptor version of a port descriptor to be obtained is selected. An indication of the port descriptor version is provided in a command to be preceded before another command used to obtain the port descriptor. The other command uses the port descriptor version to obtain the port descriptor. The port descriptor is obtained, and the port descriptor includes information relating to a port to be used in communication within the computing environment.