Abstract: A method includes asserting a field of an event flag mask register configured to inhibit an event handler. The method also includes, responsive to an event that corresponds to the field of the event flag mask register being triggered: asserting a field of an event flag register associated with the event; and based the field in the event flag register being asserted, taking an action by a task being executed by the data processor core.

Abstract: The present disclosure relates to a mirrored serial interface (MSI) for accessing peripherals through four wire serial interface. More particularly, the present disclosure is related to serial peripheral protocol with looped back mechanism in which contents of source data line are looped back onto the destination line and compared at every clock edge to ensure data sanity and to assert presence of slave and master device during and between cycles.

Abstract: A process includes controlling a current source to cause the current source to provide a plurality of different currents at different times to an output communication line of a video display interface; and acquiring a plurality of voltages corresponding to the plurality of different currents. Acquiring the plurality of voltages includes sampling a voltage of the output communication line. The process includes comparing the plurality of voltages to a plurality of voltage thresholds; and based on a result of the comparison, determining whether the video display interface is coupled to a cable-based far end termination.

Abstract: A storage device includes a non-volatile memory including a plurality of blocks, a buffer memory that stores a plurality of on-cell counts, which are generated by reading memory cells connected to a plurality of reference word lines of the plurality of blocks by using a read level, and an artificial neural network model, and a controller that inputs an on-cell count corresponding to a target block among the plurality of on-cell counts and a number of a target word line of the target block to the artificial neural network model, and infers a plurality of read levels for reading data of memory cells connected to the target word line using the artificial neural network model.

Abstract: A method and apparatus for the increase of internal data throughput and processing capability for SSD's, to enable processing of database commands on an SSD. A front-end ASIC is provided with 256 to 512 RISC processing cores to enable decomposition and parallelization of host commands to front-end module (FM) ASICs that each in turn are coupled to multiple NVM dies, as well as processing of host database operations such as insert, select, update, and delete. Each FM ASIC is architected to increase parity bits to 33.3% of NVM data, and process parity data with 14 LDPC's. By increasing the parity bits to 33.3%, BER is reduced, power consumption is reduced, and data throughput within the SSD is increased.

Abstract: An information processing apparatus according to an aspect of the present invention includes an information processing circuit configured to generate a finite state machine based on a predetermined matching condition with respect to sequence data of an event that is input to the information processing apparatus; to process the sequence data so as to substantially remove data that does not match the matching condition from the sequence data; and to output the processed sequence data.

Abstract: An embodiment of the invention may include a method, computer program product, and computer system for reconfiguration of a computing environment from an as-is input/output (I/O) configuration to a to-be I/O configuration. An embodiment may include normalizing respective hierarchical models of the as-is and the to-be I/O configurations. The hierarchical models each comprise a hierarchical structure of leaf and non-leaf nodes. Normalizing comprises the application of syntactical transformation rules to the hierarchical models such that their respective I/O configurations are defined in a syntactically consistent manner. An embodiment may include creating respective hash tree representations of the first hierarchical model and the second hierarchical model. Nodes of the hash tree representations are checksum values. Nodes of the hash tree representations reflect the hierarchical structure of their respective hierarchical models.

Abstract: Technologies are described herein for providing a Baseboard Management Controller (“BMC”) -based security processor. The disclosed BMC-based security processor can provide a hardware Root of Trust (“RoT”) for a computing platform without the addition of specialized silicon to the platform and while minimizing the number of attack points. The disclosed BMC-based security processor can also provide functionality for securely filtering requests made on certain buses in a computing platform. Through implementations of the features identified briefly above, and others described herein, various technical benefits can be achieved such as, but not limited to, increased security as compared to previous computing systems that utilize a BMC to provide a hardware RoT and reduced complexity and cost as compared to previous computing systems that utilize a separate hardware device, such as a Field Programmable Gate Array (“FPGA”) or a microcontroller, to provide a hardware RoT.

Abstract: Disclosed is a data transfer system capable of accelerating data transmission between two chips. The data transfer system includes: a master system-on-a-chip (SoC) including a master transmission circular buffer and a master reception circular buffer; and a slave SoC including a slave reception circular buffer and a slave transmission circular buffer. The slave/master reception circular buffer is a duplicate of the master/slave transmission circular buffer; accordingly, the write pointers of the two corresponding buffers are substantially synchronous and the read pointers of the two corresponding buffers are substantially synchronous as well. In light of the above, the read and write operations of the master/slave transmission circular buffer can be treated as the read and write operations of the slave/master reception circular buffer; therefore some conventional data reproducing procedure(s) for the data transmission can be omitted and the data transmission is accelerated.

Abstract: This disclosure describes system on a chip (SOC) communications that prevent direct memory access (DMA) attacks. An example SoC includes an encryption engine and a security processor. The encryption engine is configured to encrypt raw input data using a cipher key to form an encrypted payload. The security processor is configured to select the cipher key from a key store holding a plurality of cipher keys based on a channel ID describing a {source subsystem, destination subsystem} tuple for the encrypted payload, to form an encryption header that includes the channel ID, to encapsulate the encrypted payload with the encryption header that includes the channel ID to form a crypto packet, and to transmit the crypto packet to a destination SoC that is external to the SoC.

Abstract: A neural processing unit (NPU) includes a controller including a scheduler, the controller configured to receive from a compiler a machine code of an artificial neural network (ANN) including a fusion ANN, the machine code including data locality information of the fusion ANN, and receive heterogeneous sensor data from a plurality of sensors corresponding to the fusion ANN; at least one processing element configured to perform fusion operations of the fusion ANN including a convolution operation and at least one special function operation; a special function unit (SFU) configured to perform a special function operation of the fusion ANN; and an on-chip memory configured to store operation data of the fusion ANN, wherein the schedular is configured to control the at least one processing element and the on-chip memory such that all operations of the fusion ANN are processed in a predetermined sequence according to the data locality information.

Abstract: The present invention includes a CP monitoring unit configured to monitor a CP voltage applied through a CP line from the controller of the slow charging cable when the slow charging cable is connected to an inlet, a mode switching request unit configured to request mode switching to the controller of the slow charging cable by converting the monitored CP voltage to a preset mode switching voltage; a communication switching unit configured to connect a LIN transceiver for LIN communication to the CP line when the controller of the slow charging cable is switched to a LIN communication mode for software update, and a control unit configured to control the LIN transceiver to transmit a pre-stored software update file to the controller of the slow charging cable, so that the controller's software can be updated without disassembling or damaging the controller of the slow charging cable.

Abstract: A computer system is provided. The computer system includes a memory and at least one processor coupled to the memory. The processor is configured to identify a message to a plug and play (PnP) manager of an operating system, the message comprising an identifier of a device to be configured by the PnP manager, determine whether the device is targeted for device identifier translation at least in part by determining whether the device satisfies one or more target device criteria, and replace the identifier of the device with a reference identifier different from the identifier of the device in response to a determination that the device is targeted for device identifier translation, the reference identifier being usable by the PnP manager to install or configure the device.

Abstract: Provided are a method for transmitting a control instruction, a transmitting device and a receiving device. The method includes the follows. A first control instruction is obtained by a transmitting device. the first control instruction is encapsulated into a first protocol data stream. The first protocol data stream is superimposed, by the transmitting device through a first coupling network, on a second protocol data stream in the form of differential signal generated according to multimedia data to obtain a first signal, and the first signal is transmitted to a receiving device via a cable. The first signal is filtered by the receiving device to obtain a first protocol data stream, and the first protocol data stream is decapsulated to obtain a first signal. By adopting the disclosure, transmitting control instruction via the cable can realize controlling the target device connected to the receiving. The user experience is high.

Abstract: A method for configuring an interface device connected to a control device and a field device, wherein the method includes receiving a first machine learning application having a plurality of logical components connected in a pipeline, where the first machine learning application serves to analyze a signal from the field device utilizing a first machine learning model, generating a plurality of code blocks utilizing a translator based on the plurality of logical components of the first machine learning application, connecting the plurality of code blocks in accordance with the pipeline of the first machine learning application to generate a first output from the signal from the field device, and deploying the connected code blocks on firmware of the interface device including creating a virtual port connectable to the control device, and where the virtual port serves to transmits the first output to the control device.

Abstract: Facilitating ad hoc daisy-chaining of dynamically addressable devices having configurable physical layer interfaces together in a serial manner is presented herein. A system can include a group of devices communicatively coupled with respective devices of the group of devices in a daisy-chained manner via physical layer (PHY) interfaces of the respective devices including a group of available communication protocol configurations including a low voltage differential signaling (LVDS) based PHY configuration, a controller area network (CAN) based PHY configuration, and/or a single-ended serial communication PHY configuration including a complementary metal-oxide-semiconductor (CMOS) based interface or a transistor-transistor logic (TTL) based interface.

Abstract: A memory module includes a substrate, plural memory devices, and a buffer. The plural memory devices are organized into at least one rank, each memory device having plural banks. The buffer includes a primary interface for communicating with a memory controller and a secondary interface coupled to the plural memory devices. For each bank of each rank of memory devices, the buffer includes data buffer circuitry and address buffer circuitry. The data buffer circuitry includes first storage to store write data transferred during a bank cycle interval (tRR). The address buffer circuitry includes second storage to store address information corresponding to the data stored in the first storage.

Abstract: Disclosed are a storage device and a method for sudden power off recovery thereof. The method includes: performing a first snapshot operation on the storage device to obtain system information, and storing the system information and a first tag into a non-volatile memory when the storage device in an idle state; performing a second snapshot operation on the storage device to obtain system information of the storage device, and storing the system information and a second tag into the non-volatile memory when at least one of the following conditions occurring: updating a logical-to-physical mapping table in the non-volatile memory, executing a garbage collection operation, and programming a new block; searching the latest system information in the non-volatile memory when recovering supply of power; when determining that the searched system information includes the first tag, performing a lightweight sudden power off recovery operation in the storage device.

Abstract: Systems and methods for predictive performance indicators for storage devices are described. The data storage device may process host storage operations and maintenance operations that impact real-time performance. A performance value and corresponding threshold may be determined. Increases in maintenance operations and resulting changes in the performance value may be predicted. When the predicted change in performance value crosses the performance threshold, the host device may be notified.

Abstract: A processing device, operatively coupled with a memory device, is configured to receive a direct memory access (DMA) command to perform a memory access operation, the DMA command comprising a priority value; assign the DMA command to a priority queue of a plurality of priority queues based on the priority value of the DMA command; and execute a plurality of DMA commands from the plurality of priority queues according to a corresponding execution rate of each priority queue of the plurality of priority queues.