Abstract: In the method and apparatus of the present invention a file to be added to the database is given a unique name that is dependent upon the contents of the file such that, when the contents of the source file changes, the name of the database component file to be added to the database also changes. Conversely, if two files of the same name have the same information contained therein, the same file name will be generated and the duplication of information in the database is prevented by providing a simple test that checks for the existence of the name of the database file before the generation and addition of the new file to the database. If the file name exists in the database, information is already contained in the database and the file is not generated and added to the database information. Preferably the name of the file is generated by computing a hash value from the contents of the file concatenating the hash value to the name of the source file.

Abstract: The decoding of certain instructions cause an instruction unit of a production line data processing system to stall. Instructions still in the production line are executed, but no new instructions are sent into the production line until the instruction that caused the stall condition is executed. The execution of the instruction that caused the stall is completed by an execution unit taking over control of an address unit.

Abstract: A computer system for executing application programs with limited available main memory capacity includes a main memory management system. The architecture of the stub vectors of a swappable code object and the protocol for referencing the stubs in active call frames reduces the overhead time of code object swapping. The stub vectors for a swappable code object are clustered together in memory; and each cluster comprises at least one entry stub and a return stub. A return stub vector is referenced in an active call frame only when its associated code object is not resident in main memory or when the code object has been placed on probation in contemplation of moving the object out of main memory. A linked list of resident code objects is employed in the selection of objects to be removed from main memory. A number of the least recently used code objects are put on probation in anticipation of the need to swap code between main memory and bulk memory.

Abstract: The Avionics Program Expert (APEX) is an automatic code generation tool for the Ada programming language (MIL-STD 1815A). It provides the programmer using APEX with the ability to quickly create a graphical representation of his initial program design. The graphical representation used by APEX is akin to a flowchart, but the interactive capabilities of the tool make design creation much faster and more efficient. Once the programmer has created his complete (or even partial) representation of a program, Ada code can then be generated with (from) APEX. The APEX program representation provides the user with three different, yet consistent, views of his program. The first view allows the programmer to lay out his initial Ada package specifications; this view is called the APEX view. A second view allows the programmer to create and manipulate complex data structures and define local variables; this view is the Data Structure view.

Abstract: A control system and method for use with a sort accelerator having a rebound sorter as a merger in disclosed. The control system allows records to be efficiently and effectively transferred between processing elements and record storage elements of a rebound sorter. The control system allows consecutive groups of records to be sorted in the rebound sorter without mixing records from separate groups. The control system also pipelines records through the sorter by allowing different groups of records to input into the rebound sorter directly adjacent to each other.

Abstract: In a data processing multiprocessor system having distributed shared resources where each system processor (7) is provided with at least a local memory (8) to which it get access through a local bus (11), and with an interface unit (10) for connection of the local bus (11) to a system bus (5) and wherein each of the system processors may have access the local memory of another processor through its own local bus, its own interface unit, the system bus and the local bus of the other processor, deadlock is prevented by providing a bypass unit (40) of the interface unit (10) for enabling access from the system bus to the local bus through the bypass unit, a block (9) connected between the local bus and the interface unit (10) for latching system bus access requests received from an agent processor on the local bus, and a block (12) for isolation of the agent processor outputs from local bus, so that each agent processor may post read/write operations in the related latching block (9) for latching bus access requ

Abstract: A data structure for tabular data arranged in rows and columns. The data structure includes a header portion including a generic columnar processing information table, and a data portion for storing data in rows, the data portion further identifying a table containing generic columnar processing information to be used in processing selected cells in the row. In a refinement, each row in the data structure includes a row header including a row number and at least one cell, the row number identifying a row in a table for the cell. As a further refinement, each cell includes a header portion and a value portion, the header portion containing a cell number identifying a column in a table for the cell.

Abstract: A multi-processing system of the type having a plurality of MSUs is provided with a support controller in each MSU. Each of the MSUs is provided with a plurality of the interface registers, one for each associated MSU to be connected to the master MSU. Each support controller in each MSU is provided with an initial program load (IPL) controller and each IPL controller is provided with a scan settable control coupled to an external keyboard or console which permits unique scan settable information to be loaded into the IPL controller for setting the interface registers and for interconnecting the MSUs in a desired multi-processing configuration.

Abstract: A computer system with an emulation mechanism includes a program execution unit for executing an application program. The application program includes a write command. An emulation control unit writes an address and data concerning a write command in buffers in response to the write command. When a predetermined condition is satisfied, the emulation control unit generates and outputs an interrupt to the program execution unit. In response to the interrupt, the program execution unit executes an emulation program and emulates the address and data stored in the buffers upon execution of the emulation program.

Abstract: Interprocessor message communication and synchronization apparatus and method for a plurality of processors connected to a system bus. The message communication photocol involves utilizing an array of mailbox locations associated with the processors, respectively, and located in common memory accessible to all of the processors. A processor desiring to send a message to another processor inserts the message into its mailbox along with the address of the other processor. The sending processor interrupts the receiving processor which, in response to the interrupt, scans the mailboxes to find the mailbox with its address therein thereby receiving the message. The interrupt is effected by the sending processor broadcasting an input/output write instruction on the system bus along with the address of the receiving processor and a data field representative of the interrupt to be transmitted.

Abstract: An improved system for interconnecting main storage units is provided wherein each main storage unit is provided with a support control card and each support control card is provided with interface connection means comprising X-1 number of interfaces where X is a value equal to the number of MSUs. And means for enabling the connection of the interfaces between different pairs of MSUs to operably connect any number of said X number of MSUs to a plurality of data processors employing X(X-1)/2 pairs of cables.

Abstract: Power may be conserved and battery life may be extended in a microprocessor controlled device by providing two microprocessors, one of which is a low power, low performance low speed processor for performing background tasks, the other of which is a high power, high performance, high speed processor for performing computationally intensive foreground tasks. The low speed processor activates the high speed processor when a high performance task is to be performed. When activating the high performance processor, the low performance processor also controls the device's power supply to provide high voltage to the high speed processor. The high speed processor may run at variable clock speeds, with power consumption of the processor increasing with increasing speed. The high speed processor selects its own clock speed based upon the task to be performed, by including a clock speed in each software subroutine which controls a task.

Abstract: A microcomputer in which a higher address must be corrected according to a carry or borrow signal generated during address computation for memory reference based on each addressing mode. The microcomputer is provided with a databank register for holding the higher address and a temporary register for storing a value obtained by incrementing or decrementing by one digit the contents of the data bank register so that the higher order address may be corrected with neither increase in the number of instruction executing cycles nor loss of the memory area continuity.

Abstract: The present invention provides to the software application the verification and license check out functions which are normally performed by a license server of a network software license system. The encrypted license information is contained in a license token, and is sorted in the database controlled by the license server. In contrast to the prior art where the license server either grants or denies the request after verifying the user's credentials, the license server in the preferred embodiment of the present invention finds the correct license token for the software application and transmits the license token to the licensing library. In application specific license access module attached to the application decodes the licensing token. Routines in the licensing library coupled to the software application verify the license information before checking out the license and updating the license token.

Abstract: A computer system especially for solution of real time inference problems is disclosed. The system includes a systolic cellular processor which provides predictable and responsive real time operation and fine grain programmability. The system comprises a plurality of separate processor cells each having its own local memory, the cells running simultaneously and operative to execute their respective program instructions. A global memory is coupled via a global bus to the processor cells and provides data to the cells and stores data from the cells. The bus provides effectively simultaneous access of all cells to the global memory. A further feature of the system is a novel parallel programming language using English syntax and which provides synchronous and predictable binding of code to each cell. A graphic work station is provided as a user interface to provide visual access to each cell or to cell groups for ease of control.

Abstract: A circuit is provided for control and data transfer between a standard data storage device interface and one of a choice of several host computers. Parallel transition memories in conjunction with a buffer memory under common control of a buffer manager increase the transfer efficiency between the data storage unit and the host computer. Selectable register banks provide interface compatibility with multiple host computers for implementation of the invention.

Abstract: A computer system having plural nodes interconnected by a common broadcast bus. Each node has memory and at least one node has a processor. The system has a dynamically configurable memory which may be located within the system address space of a distributed system architecture including memory within each node having a processor and the memory resident within other nodes. The memory in the system address space is addressable by system physical addresses which are isolated from the physical addresses for memory in each node. The node physical addresses are translatable to and from the system physical addresses by partition maps located in partition tables at each node. Memory located anywhere in the distributed system architecture may be partitioned dynamically and accessed on a local basis by programming the partition tables, stored in partitioning RAMs.

Abstract: In pyramidal data storage, a single address is used to identify any arbitrary large group of related data. The data items are stored in the form of multi level progressions in which lower level data items are combined to form higher and higher level data items in the form of a pyramid. The invention provides a method and apparatus to store and retrieve pyramidal data groups from a computer memory.

Abstract: A reduction in the number of cycles required to obtain data from main storage when a "miss" occurs in a cache for a desired line of data but a match to another line from the same page of data in main storage as the desired line is present in the cache. In accordance with the present invention if a match to another line from the same page is present, the real address for the other line from the same page is used to fetch the desired line of data directly from the main storage without an address translation. This technique works for a virtually addressed cache whose directory contains both a virtual and a real address for every line of data stored in the cache.

Abstract: A pipelined processing unit includes an instruction unit stage containing resource conflict apparatus for detecting and resolving conflicts in the use of register and indicator resources during the different phases of instruction execution. The instruction unit includes a plurality of resource registers corresponding in number to the number of instructions which can be processed concurrently by the processing unit. Decode circuits in response to each new instruction received by the instruction unit generate one or more sets of bit indication signals designating those resources required by the specific pipeline stage(s) executing the instruction for completing the execution of the instruction which are shared by those stages capable of completing the execution of instructions.