Abstract: A hashing data storage and retrieval arrangement whose storage capacity is unaffected by collisions. A first memory serves as a hash index table, for storing pointers at each address location corresponding to a hash value generated by hashing a key data word. Each pointer is the address of a location in a second memory, which has a separate storage location for each key data word, its associated data, and a further pointer which is the address of the next key data word resulting from a collision during hashing. Preferably a pipeline register between the two memories permits hashing of a subsequent key data word while accessing of the second memory is still in progress.
Abstract: A method and apparatus for compressing dictionary database information is described. The method divides the database information into a number of parts which are each conducive to a predetermined compression technique. A first part database is formed consisting of all the entry points in the dictionary wherein each entry point is associated with a unique word number. A second part database is formed consisting of a multiplicity of placeholders. A third part database is formed consisting of all the entry points of the dictionary in the exact order in which they appear in the dictionary. A fourth part database is formed consisting of the definitions and usage notes without reference to their text. A fifth part database allows retrieval of articles of interest without having to decompress the entire dictionary. Compression techniques using multigrams and minimum-redundancy codes are selectively applied to the different database parts.
Type:
Grant
Filed:
October 22, 1990
Date of Patent:
July 26, 1994
Assignee:
Franklin Electronic Publishers, Incorporated
Abstract: A programmable controller has a function for referring to a reference clock signal every cycle time and updating the present value of a count in a user timer upon confirming that the reference clock signal has changed state. An execution time of a user program is measured from the start of execution thereof in each cycle time, and it is determined whether the measured execution time has exceeded a minimum unit time of the reference clock signal, such that the present value of the count in the user timer is updated even if the minimum unit time has been exceeded. As a result, the present value of the user timer count can be updated with certainty even if the user program execution time is so long that the minimum unit time is exceeded.
Abstract: This invention encodes information (such as the field values of a database record, or the words of a text document) so that the original information may be efficiently searched by a computer. An information object is encoded into a small "signature" or codeword using a method. A base or "leaf" signature S1 34 is computed by a known technique such as hashing. The logical intersection (AND) of each possible combination of pairs of bits of the base signature is computed, and the result is stored as one bit of a longer combinatorial signature CS1 42. The bit-wise logical union (bit-OR) of the combinatorial signatures of a group of records produces a second-level combinatorial signature CS2 52 representing particular field values present among those records. Higher-level combinatorial signatures CS3 60, CS4, etc. are computed similarly.
Type:
Grant
Filed:
February 19, 1992
Date of Patent:
June 7, 1994
Assignee:
International Business Machines Corporation
Abstract: A system and method for connecting electronic spreadsheets through a local area network are provided in which the spreadsheet programs are separate from the databases upon which they operate. The databases are multidimensional with each cell or datum identified by a unique set of element identifiers. The system and method allow users to create and control their own spreadsheet models while working with one, consistent pool of information. Changes in data effected by one user are reflected in the spreadsheets of all users, thereby guaranteeing consistent results for an entire work group at all times. Access restriction parameters for each user for each element of each dimension of the database also are provided. Multiple levels of consolidation values for each dimension of the database are calculated and updated automatically.
Abstract: Methods and apparatus for immunizing dynamic random access memory (DRAM) modules in the data processing system against data loss from transitions that occur with memory mode switching during the scan operation and permitting normal operations to be performed on the memory modules regardless of the state of the system clocks.
Type:
Grant
Filed:
July 3, 1990
Date of Patent:
May 17, 1994
Assignee:
Digital Equipment Corporation
Inventors:
Kumar Chinnaswamy, Hansel A. Collins, Michael B. Evans, Timothy P. Fissette, Michael A. Gagliardo, John J. Lynch, James E. Tessari
Abstract: A system and method for automatically and optimally determining a route to be wired in a Programmable Logic Device (PLD) are disclosed in which a plurality of load pins to be wired with a source pin are selected sequentially according to a shortest length of distance from the source pin to the respective load pins, a plurality of switching stations present midway through each route of paths are selected on the basis of coordinates of a center of gravity derived from the coordinates of the unwired load pins and distances to the respective load pins to be wired sequentially, and, thus, a line network constituted by the routes of the first and second paths is formed. Furthermore, the route is corrected by searching out any of problematic switching stations through which the path cannot be formed from among the switching stations present along the route so as to bypass the problematic switching station.
Abstract: A circuit module includes one or a plurality of semiconductor parts, a substrate having the semiconductor parts mounted thereon, and terminals arranged on an outer periphery of the substrate along a plurality of sides of said substrate. The circuit module is connected to a board of a computer by plugging the terminals into corresponding terminal holes, so that the terminals are used in common for providing electrical connection and mechanical connection with the board of the computer.
Type:
Grant
Filed:
June 27, 1990
Date of Patent:
April 26, 1994
Assignee:
Mitsumi Electric Co., Ltd.
Inventors:
Isao Okada, Yoshiyuki Kato, Koji Ide, Toshihiko Yasuma, Richard G. Geiger, Akio Tanaka, Ryuichi Sada, Mikito Baba
Abstract: A system and method for database management for providing support for long-term storage and retrieval of objects created by application programs written at least in part in object-oriented programming languages consists of a plurality of software modules. These modules provide data definition language translation, object management, object translation, and persistent object storage service. Such system implements an object fault capability to reduce the number of interactions between the application, the database management system, and the database.
Type:
Grant
Filed:
May 30, 1990
Date of Patent:
March 22, 1994
Assignee:
Texas Instruments Incorporated
Inventors:
Thomas J. Bannon, Stephen J. Ford, Vappala J. Joseph, Edward R. Perez, Robert W. Peterson, Diana M. Sparacin, Satish M. Thatte, Craig W. Thompson, Chung C. Wang, David L. Wells
Abstract: An interruption signal from a common input/output device is coupled to all processors through a common bus, and each processor issues to the common bus its own interruption receipt acceptance or negation state and the respective processors watch and decide individually interruption receipt acceptance or negation states on the common bus of the individual processors. Only one of processors which are ready to accept the receipt of interruption is allowed to accept the receipt of an interruption signal from the common input/output device in accordance with a predetermined priority.
Abstract: Selected memory locations of a buffer memory having an m x n address space are loaded each with a trigger code. First and second data words, in bits and n bits respectively, are used to read the numerical value stored at a memory location of the buffer memory. If the numerical value bears a predetermined relationship to the trigger code, a predetermined response signal is generated.
Abstract: A method and system are disclosed which permits the self modification of data stream constructs by the utilization of one or more macro definitions, each of which includes a plurality of parameters, at least one of which is modifiable. A modify parameter structured field is included within a selected macro definition and identifies a particular parameter within the macro definition which may be modified. Subsequent invocation of the macro definition may include selective identification of a parameter to be modified. If the identified parameter has been specified as modifiable by the macro definition, the parameter is modified and the macro definition is thereby altered. In this manner the present method permits the utilization of a single macro definition by multiple processes within a data stream.
Type:
Grant
Filed:
June 23, 1993
Date of Patent:
March 1, 1994
Assignee:
International Business Machines Corporation
Inventors:
Barbara A. Barker, Thomas R. Edel, Jeffrey A. Stark
Abstract: A method and system for controlling mutually exclusive resources and for preventing deadlocks in a multi-tasking computer system by generating a graph containing nodes to which are mapped the tasks included in a flow of processes and the critical resources which may be appropriated by at least one of the tasks. The nodes of tasks executed sequentially are arranged sequentially; the nodes of tasks executed in parallel are arranged in parallel with each other and each node of a critical resource is arranged in parallel with every node which may appropriate it. Every time a signal to being execution of a task is transmitted, a token is generated in the task node and the critical resource node is parallel with the task node.
Type:
Grant
Filed:
February 12, 1990
Date of Patent:
February 1, 1994
Assignee:
International Business Machines Corporation
Abstract: A data processor, such as a digital signal processor, that has augmented memory, I/O and math units for real-time performance of complex functions, is placed under the control of a group of abstract object-oriented modules arranged with an underlying operational nucleus that includes a real-time kernel. The modules are hierarchically configured, with the lowest being an array object type that references memory allocations. A stream object type, based on the arrays, defines channels between application software and data devices. A vector object type, also based on the arrays, establishes structure within allocated blocks and also enables vector math functions to be undertaken by the vector module. Matrix and filter object types utilize the arrays and vectors in sequences controlled by the corresponding matrix and vector modules.
Type:
Grant
Filed:
October 2, 1989
Date of Patent:
February 1, 1994
Assignee:
Spectron Microsystems, Inc.
Inventors:
Robert E. Frankel, David M. Lindsay, David A. Russo, David Y. Wong
Abstract: A data structure for tabular data arranged in rows and columns. The data structure includes a header portion including a generic columnar processing information table, and a data portion for storing data in rows, the data portion further identifying a table containing generic columnar processing information to be used in processing selected cells in the row. In a refinement, each row in the data structure includes a row header including a row number and at least one cell, the row number identifying a row in a table for the cell. As a further refinement, each cell includes a header portion and a value portion, the header portion containing a cell number identifying a column in a table for the cell.
Abstract: Communication-control equipment having data-processor, primary storage for storing process data of the data-processor, secondary storage for storing DMA data as well as the process data, and DMA bus for transferring only the DMA data communicated between the secondary storage and a transmission or receiving buffer. The data-processor can communicate with the primary storage during DMA data transfer, because the DMA data are transferred through the DMA bus and so the address bus and data bus connecting data-processor and the primary storage are available during the DMA transfer.
Abstract: A digital data processing system having an index file containing a plurality of file headers includes an arrangement having a file header processing portion for iteratively retrieving file headers from an index file and for establishing in response thereto a descriptor defining a directory in a directory tree, each descriptor defining the relationship of the corresponding directory to a parent directory in the directory tree, and a group vector processing portion, responsive to processing of a file header by the file header processing portion, for generating a group vector comprising a plurality of pointers to said descriptors, each pointer defining the relationship of a directory to one or more child directories in said directory tree.
Abstract: According to an assigning method and its apparatus having a resource use recording section for recording a use state of a resource necessary for executing given operations, a functional unit possession recording section for recording information representing an inexecution functional unit, and an operator information management section for storing an operation executable by each functional unit and a clock count necessary for executing the operation, in order to assign an operation selected from the operations (by the operation selection step) to an optimal functional unit, the use state of the resource is checked from the resource use recording section (with reference to the usable resource decision step), the operation executable functional unit is found from the operation unit possession recording section (by the operation assignable unit decision step).
Abstract: A character pattern data holding circuit includes a through latch. In a mode other than a character display mode, a gate of the through latch is opened according to an access command from the main system by making use of a data function of the through latch so that the main system and a second memory are directly connected to each other. In this way, display control timing restrictions are not imposed on the main system and access performance is enhanced.
Abstract: A method and apparatus for addressing compressed nodes in a database structure is disclosed in which each compressed node is associated with a particular mapping function and each element in the node is assigned a particular identification code. The character to be searched is converted into a physical address having a first portion which is used to index to a particular element in a compressed node, and a second portion which is used to verify that the selected element corresponds to the search character.