Patents Examined by John F. Guay
  • Patent number: 5914523
    Abstract: A semiconductor device, polysilicon-contacted trench isolation- structure that provides improved electrical isolation stability, a method of operating a polysilicon-contacted trench isolated semiconductor device, and a process for manufacturing a polysilicon-contacted trench isolation structure. The trench isolation structure includes an isolation trench formed in a semiconductor substrate. The isolation trench has a layer of trench lining oxide, a layer of trench lining silicon nitride and a trench fill polysilicon (poly 1) layer. Exposed lateral surfaces of the poly 1, which extend above the trench lining silicon nitride, are contacted to another layer of polysilicon (poly 2). The method of operation includes applying a bias voltage to the trench fill poly 1 layer via poly 2. The process for manufacture includes etching an isolation trench that extends through a layer of field oxide and into a semiconductor substrate.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: June 22, 1999
    Assignee: National Semiconductor Corp.
    Inventors: Rashid Bashir, Wipawan Yindeepol
  • Patent number: 5898188
    Abstract: The side surfaces of an active layer from which a thin-film transistor is constructed are annealed by laser light irradiation. Defects which occur during patterning concentrate at the side surfaces of the active layer, and due to the movement of carriers which results from these defects, an OFF current is generated. Thus, by improving the crystallinity of the side surfaces of the active layer and thereby reducing the number of defects it is possible to reduce the OFF current.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: April 27, 1999
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Hideomi Suzawa, Satoshi Teramoto
  • Patent number: 5895939
    Abstract: A vertical SiC trench MOSFET power switching FET includes a gate electrode in the trench. The MOSFET adds a buried region of a first conductivity type, more heavily doped than a base layer of the first conductivity type, to the base layer except adjacent to the trench. The buried region is preferably disposed in the base layer, or between a drift layer of a second conductivity type and the base layer. The region of the first conductivity type is optionally disposed below the bottom of the trench to encourage expansion of the depletion layer of the MOSFET. A depletion-type vertical SiC MESFET of the invention includes a buried region of the first conductivity type in a base layer of a second conductivity type. A Schottky electrode on a portion of the base layer above the buried region ensures adequate expansion of a depletion layer.
    Type: Grant
    Filed: April 9, 1998
    Date of Patent: April 20, 1999
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Katsunori Ueno
  • Patent number: 5874753
    Abstract: In a field effect transistor including active layers having a heterojunction structure with at least two different semiconductor materials, a layer for supplying electrons is disposed opposite a drain electrode, in contact with a region of the active layers including a dopant impurity producing n type conductivity. Therefore, degradation of the electrical characteristics caused by trapping of electrons in a drain ohmic contact layer due to fluorine diffusing into the semiconductor layers is suppressed by supplying electrons from the layer opposite the drain electrode, thereby improving reliability of the field effect transistor including the heterojunction structure.
    Type: Grant
    Filed: March 26, 1997
    Date of Patent: February 23, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Norio Hayafuji, Yoshitsugu Yamamoto
  • Patent number: 5874768
    Abstract: A high breakdown voltage semiconductor device formed in an SOI structure is disclosed. An MOS transistor composed of a drift layer, p well, a source, a gate, and a drain is formed in an island region surrounded by insulators on a semiconductor substrate. Furthermore, an electricfield-alleviating layer is formed in a bottom portion of the Si island region. The electric-field-alleviating layer is a semiconductor layer of exceeding low concentration, e.g., intrinsic, and therefore a virtual PIN structure is structured among the p well and the drift layer. Because the electric-field-alleviating layer corresponds to an I layer of the PIN structure, a depletion layer is created within the electric-field-alleviating layer when high voltage is applied to the MOS transistor, the high voltage is distributed throughout this depletion layer, and high breakdown voltage can be obtained.
    Type: Grant
    Filed: November 7, 1997
    Date of Patent: February 23, 1999
    Assignee: Nippondenso Co., Ltd.
    Inventors: Hitoshi Yamaguchi, Hiroaki Himi, Seiji Fujino
  • Patent number: 5869856
    Abstract: Disclosed is a field effect transistor which has: an operating layer which is of a compound semiconductor; a first conductive layer which is formed as a channel layer; a second conductive layer which is formed below the first conductive layer and through which a current less than that flowing through the first conductive layer is flown; an ohmic electrode which is ohmic-junctioned with the second conductive layer; and a source electrode and a drain electrode which are junctioned with the first conductive layer; wherein the source electrode and the drain electrode are ohmic-junctioned with the ohmic electrode with a resistivity lower than the resistivity between the first conductive layer and the second conductive layer.
    Type: Grant
    Filed: December 24, 1996
    Date of Patent: February 9, 1999
    Assignee: NEC Corporation
    Inventor: Kensuke Kasahara
  • Patent number: 5847436
    Abstract: A bipolar transistor includes a chip having a base electrode and an emitter electrode on a surface thereof and a film resistor provided on a surface of the chip and electrically connecting the base electrode and the emitter electrode to each other, the film resistor having a negative resistance characteristic with temperature change.
    Type: Grant
    Filed: April 29, 1997
    Date of Patent: December 8, 1998
    Assignee: Kabushiki Kaisha Tokai Rika Denki Seisakusho
    Inventor: Hitoshi Iwata
  • Patent number: 5841170
    Abstract: A field effect transistor is fabricated on an SOI substrate. N-type source and drain regions are arranged apart from each other in a semiconductor thin film of the SOI substrate. A P-type channel region is formed between the source and drain regions. Moreover, a gate electrode is formed over the channel region to cover the channel region through a gate oxide film. Extreme portions of the channel region, adjacent to the source and drain regions, have higher doping concentrations than in a center portion thereof. Furthermore, the gradient of the doping profile in the channel region is adjusted so as to reduce the current gain of a parasitic transistor in the field effect transistor. This structure enables a reduction of the channel length of the field effect transistor to the sub-half-micron order without deteriorating the electrical characteristics of the field effect transistor.
    Type: Grant
    Filed: January 14, 1997
    Date of Patent: November 24, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Alberto Oscar Adan, Seiji Kaneko
  • Patent number: 5838022
    Abstract: Time coefficient .beta., voltage coefficient d and temperature coefficient .phi..sub.0 of a jumbo TFT including a plurality of TFTs connected parallel to each other and manufactured under the same condition are obtained through experiment using -BT stress test, mean value .mu. and standard deviation .sigma. of the threshold voltage shift amount are calculated by -BT stress test for a plurality of individual TFTs, and the life t of the individual TFT is evaluated by the expression.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: November 17, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Shigenobu Maeda
  • Patent number: 5831296
    Abstract: Disclosed is a semiconductor device comprising an undoped GaAs layer, an intermediate undoped layer and an undoped Ga.sub.1-x Al.sub.x As layer which are successively provided on a substrate made of a semiinsulating GaAs crystal; the intermediate undoped layer being an undoped In.sub.y Ga.sub.1-y As layer, an undoped GaAs.sub.1-z Sb.sub.z layer, a superlattice layer which includes an undoped In.sub.y Ga.sub.1-y As layer and an undoped GaAs.sub.1-z Sb.sub.z layer, a superlattice layer which includes an undoped In.sub.y Ga.sub.1-y As layer and an undoped GaAs layer, or a superlattice layer which includes an undoped GaAs.sub.1-z Sb layer and an undoped GaAs layer. When applied to a high electron mobility transistor, this semiconductor device affords a high current and a high speed and has the merit of a small dispersion in the threshold voltage thereof.
    Type: Grant
    Filed: April 28, 1994
    Date of Patent: November 3, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Takao Kuroda, Yasuhiro Shiraki
  • Patent number: 5811865
    Abstract: A method is provided for forming an improved device dielectric of a semiconductor integrated circuit, and an integrated circuit formed according to the same. For scaling geometries for use in the submicron regime, a composite dielectric layer used as a device dielectric is formed over a plurality of active areas adjacent to a field oxide region. The composite dielectric layer is formed before the field oxide region is formed and comprises a non-porous silicon nitride layer. The non-porous silicon nitride layer preferably comprises a thin deposited silicon nitride layer overlying a thin nitridized region of the substrate. The silicon nitride layer is partially oxidized during the subsequent formation of a field oxide region between the plurality of active areas. An oxide layer may be formed over the silicon nitride layer before the formation of the field oxide region which will then be densified during the field oxide formation.
    Type: Grant
    Filed: December 16, 1996
    Date of Patent: September 22, 1998
    Assignee: STMicroelectronics, Inc.
    Inventors: Robert L. Hodges, Frank R. Bryant
  • Patent number: 5811843
    Abstract: A field effect transistor includes a semi-insulating III-V compound semiconductor substrate; a channel layer disposed on the substrate; an n type electron supply layer disposed on the channel layer and comprising a mixed crystalline compound semiconductor layer including AlAs; an n type ohmic contact layer disposed on the electron supply layer; source and drain electrodes disposed on the ohmic contact layer; an opening in a region between the source and drain electrodes penetrating the ohmic contact layer; a gate electrode disposed in the opening and making a Schotty contact; and a surface protection film of a semiconductor material free of Al, In, and As, covering the opening except where the gate electrode is present. Fluorine is prevented from getting into the electron supply layer with no increase in transconductance or source resistance by providing a layer between the source and a channel, and between the gate and the channel.
    Type: Grant
    Filed: February 24, 1997
    Date of Patent: September 22, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshitsugu Yamamoto, Norio Hayafuji
  • Patent number: 5773850
    Abstract: After the removal of a native oxide layer on a surface of an InP substrate, a ZnCdSe buffer layer is grown, and a ZnSeTe layer as a II-VI compound semiconductor layer containing Te is formed on the ZnCdSe buffer layer. This permits the ZnSeTe layer to grow two-dimensionally from directly after the start of growing such that its crystal quality is considerably improved. In this manner, a semiconductor device is attained which has above the InP substrate the II-VI compound semiconductor layer containing Te, which has such a high quality as to permit the semiconductor device to be used as a light emitting device.
    Type: Grant
    Filed: May 7, 1997
    Date of Patent: June 30, 1998
    Assignee: NEC Corporation
    Inventor: Koichi Naniwae
  • Patent number: 5736754
    Abstract: An organic full color light emitting diode array including a plurality of spaced apart, electrically conductive strips formed on a semiconductor substrate, a plurality of cavities defined on top of the strips and three electroluminescent media designed to emit three different hues deposited, along with light transmissive electrical conductors, in the cavities. A transparent dielectric material is formed to seal each of the cavities. The semiconductor substrate is, for example, a CMOS substrate and drivers for the diode array are formed in the substrate.
    Type: Grant
    Filed: November 17, 1995
    Date of Patent: April 7, 1998
    Assignee: Motorola, Inc.
    Inventors: Song Q. Shi, Franky So
  • Patent number: 5672888
    Abstract: An active layer is sandwiched between a first gate electrode and a second gate electrode, and an offset region is disposed in overlying and underlying relation to a third gate electrode and a fourth gate electrode, respectively, resulting in a double-gate structure that is effective to produce a large ON current and a low leakage current. Storage capacitances for suppressing a reduction in a pixel potential are formed between a transparent pixel electrode and a third storage capacitance electrode, between the third storage capacitance electrode and a second storage capacitance electrode, and between the second storage capacitance electrode and a first storage capacitance electrode. Large storage capacitances are thus formed in a small area.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: September 30, 1997
    Assignee: NEC Corporation
    Inventor: Kenichi Nakamura
  • Patent number: 5670801
    Abstract: A method of fabricating a semiconductor device includes producing a collector layer, a base layer, and an emitter layer on a semiconductor substrate; producing a dummy emitter electrode on a region of the emitter layer; forming a first resist except where the dummy emitter electrode is present; completely removing the dummy emitter electrode to expose the surface of the emitter layer; depositing an emitter electrode material on the first resist and the emitter layer that is exposed by the removal of the dummy emitter electrode; forming a mask on a region of the emitter electrode material film where an emitter electrode is later produced; and etching the emitter electrode material film using the mask; and removing the first resist, thereby producing an emitter electrode layer, a peripheral side part extending upward from the bottom part, and an upper fringe part protruding outward from the peripheral side part perpendicular to the peripheral side part.
    Type: Grant
    Filed: January 3, 1996
    Date of Patent: September 23, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hirofumi Nakano
  • Patent number: 5598016
    Abstract: Disclosed is a photoelectric conversion device in which a photodiode capacitance is increased. A transparent electrode is formed between a reflecting plate and a photodiode constituting a unitary picture element of a CCD image sensor. It is so formed that light is incident from the rear surface and the loop of the standing wave of the light comes on a platinum silicide film, thereby achieving the effective absorption of the incident light. The transparent electrode is formed between the reflecting plate and the photodiode in opposition to the platinum silicide film. The capacitance between the transparent electrode and the platinum silicide film can be utilized as photodiode capacitance.
    Type: Grant
    Filed: December 16, 1994
    Date of Patent: January 28, 1997
    Assignee: NEC Corporation
    Inventors: Akihito Tanabe, Shigeru Tohyama
  • Patent number: 5563444
    Abstract: A transportable object having, in a plastic support, a cavity for receiving a micromodule unit containing a conductive chip with zones electrically insulated from one another and to which is electrically connected an integrated semiconductor circuit having at least a storage function. The cavity has a contour shaped in a sequence of contiguous arcs of small amplitude relative to a median contour line of a shape matched to the shape of the chip. The contour of the cavity forms a clearance angle of 10 degrees relative to a direction perpendicular to the surface of support.
    Type: Grant
    Filed: April 6, 1994
    Date of Patent: October 8, 1996
    Assignee: Gilles Leroux, DS.A.
    Inventors: Gilles Leroux, Simon Ormerod
  • Patent number: 5548142
    Abstract: A solid-state imaging device capable of removing undesired influences, includes a semiconductor substrate having one of conductive types, a well layer arranged on the substrate and having the other conductive type opposite to the substrate, photo-sensitive pixels recessed in a matrix having a predetermined number and having the conductive type opposite to the well layer to generate signal charges corresponding to an incident light amount, a transfer channel formed along one direction of the photosensitive pixels arranged by the conductive type as the same as that of the substrate to transfer the signal charges generated by the photosensitive pixels, an electrode provided to the transfer channel on a side opposite to the substrate to supply an electric field to the transfer channel, and a barrier well formed of the impurity semiconductor material of the conductive type opposite to the conductive type of the semiconductor substrate in the manner that an impurity density of the well layer becomes longer along th
    Type: Grant
    Filed: May 17, 1995
    Date of Patent: August 20, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenichi Arakawa
  • Patent number: 5521420
    Abstract: An electrical apparatus having a top and a bottom is described. A right side portion comprised of a first substrate of semiconductor material is provided. A left side portion of a second substrate of semiconductor material comprising an integrated circuit is provided. A middle portion between the right side portion and the left side portion is provided. The middle portion is comprised of an insulative coating. A metallic interconnecting structure is provided that electrically couples the first substrate of the right side portion to the integrated circuit of the left side portion. The metallic interconnecting structure extends over the insulative material of the middle portion. A top portion comprised of the insulative material is provided that covers the integrated circuit, the metallic interconnecting structure, the left side portion, the right side portion, and the middle portion. The top portion and the middle portion sandwich the metallic interconnecting structure.
    Type: Grant
    Filed: July 5, 1994
    Date of Patent: May 28, 1996
    Assignee: Micro Technology Partners
    Inventors: John G. Richards, Hector Flores, Wendell B. Sander