Abstract: The use of a conductive reactive braze material, loaded in via holes of a diamond substrate and heated in a suitable temperature range, results in conductive vias with excellent adherence to the via hole in the diamond material. Cracking of the diamond substrate, and loose or lost via elements, are minimized. A form of the disclosure is directed to a method for producing a circuit board having a multiplicity of conductive vias. A generally planar diamond substrate is provided. A multiplicity of via holes are formed through the substrate. The holes are loaded with a conductive reactive braze material. The braze material and the substrate are heated to a temperature which causes the braze material to melt and to react with the inner surface of the via holes and bond thereto.

Abstract: A base layer interposed between an n-type GaAs collector layer and an n-type AlGaAs emitter layer is composed of a p-type InAlGaAs. From a collector/base interface to an emitter/base interface, an InAs composition of the base layer is decreased and a concentration of carbon as a p-type impurity thereof is increased so as to obtain a built-in internal field intensity in the base layer by a cooperative effect of the graded-bandgap and the impurity concentration gradient, thus reducing a base transit time of electrons. The base layer is fabricated according to MOMBE using TMG as a gallium source, controlling the InAs composition, so that a desired carbon concentration gradient is automatically formed. Thereby, a high performance heterojunction bipolar transistor with an increased built-in internal field intensity in the base layer is obtained.

Abstract: A semiconductor chip includes a semiconductor substrate having opposite front and rear surfaces and an active element on the front surface and a supporting substrate supporting the semiconductor substrate and disposed on the rear surface of the semiconductor substrate. The supporting substrate includes a radiating layer for radiating heat generated by the active element and disposed on a part of the rear surface of the semiconductor substrate directly opposite said active element and a plated metal layer of Rh, Pt, or Ni-B-W having a linear thermal expansion coefficient approximately equal to that of the semiconductor substrate and disposed on part of the rear surface of the semiconductor substrate but not directly opposite the active element. In this structure, the curvature of the chip during die-bonding is reduced. The plated metal layer is produced in a relatively simple process with no difficulty in controlling the composition of a plating solution.

Abstract: A heterojunction bipolar transistor (HBT) structure is configured so that the heterojunction between hexagonal and cubic materials is electrically active. A first embodiment of the HBT structure comprises both hexagonal and cubic silicon carbide (SiC). The emitter region is fabricated from the higher bandgap hexagonal SiC appropriately doped. The base and collector regions are grown using the lower bandgap cubic SiC. A second embodiment of the HBT structure comprises both a solid solution of SiC material such as an alloy of silicon carbon aluminum nitrogen (SiCAlN) grown upon a substrate of hexagonal SiC. The emitter region can be placed either on the top or bottom of the second embodiment of the HBT structure. Also, the bandgap between the emitter and base regions of the second embodiment can be varied by controlling the mole fraction ratio between the constituent parts of the SiCAlN, i.e., between the SiC and the AlN.

Abstract: A method is described for fabricating a lightly doped drain MOSFET integrated circuit device. The method begins by forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide, a polysilicon layer and a refractory metal silicide. A thin silicon nitride layer is formed over each of the structures and the exposed surfaces therebetween of the substrate. A pattern of lightly doped regions in the substrate is formed by ion implantation using the polycide gate structures as the mask. A dielectric spacer structure is formed upon the sidewalls of each of the polycide gate structures and over the adjacent portions of the substrate. A pattern of heavily doped regions in the substrate is formed by ion implantation using the polycide structures with spacer structures as the mask to produce the lightly doped drain source/drain structures of an MOSFET device.

Abstract: A multichip module includes: a) a multichip module substrate; b) a first chip, the first chip having opposed base and bonding faces, the base face being adhered to the multichip module substrate, the first chip bonding face including a central area and a plurality of bonding pads peripheral to the central area; c) a second chip, the second chip having opposed base and bonding faces, the second chip bonding face including a central area and a plurality of peripheral bonding pads; d) a first/second adhesive layer interposed between and connecting the first chip bonding face and the second chip base face, the first/second adhesive layer having a thickness and a perimeter, the perimeter being positioned within the central area inside of the peripheral bonding pads; e) a plurality of first loop bonding wires bonded to and between the respective first chip bonding pads and the multichip module substrate, the respective first bonding wires having outwardly projecting loops of a defined loop height, the thickness of

Abstract: In a semiconductor device having I.sup.2 L gate, on a first conducting type semiconductor layer, a first semiconductor region with a second conducting type and a wider band gap than that of the semiconductor layer and a second semiconductor region with a second conducting type and a narrower band gap than that of the semiconductor layer are formed, and on the second semiconductor region, a third semiconductor region with the first conducting type is formed.

Abstract: A heterojunction acoustic charge transport (HACT) device having a charge transport layer 16 surrounded by upper and lower charge confinement layers 14,30, respectively, and having a cap layer 36 at the outer surface, above the upper confinement layer 30, is provided with a P-N junction to minimize the effects of surface states. An intermediate layer 34 is disposed between the cap layer 36 and upper charge confinement layer 30. The upper confinement layer 30 and intermediate layer 34 are doped with opposite polarities to provide a P-N junction which creates a built-in electric field having sufficient strength to keep mobile charge carriers, transported by a SAW along the charge transport channel, from being trapped by or recombined with surface states at the external interface of the cap layer 36. Alternatively, the intermediate layer is not present and a cap layer 42 is doped to provide one side of the P-N junction.