Abstract: A master-slice type semiconductor device according to the present invention comprises a cell array on a main surface thereof, the cell array is constituted into a shape of matrix by adjoining channel regions each other, and the channel region has one of a P-channel type and a N-channel type. The cell array is constituted by a plurality of column patterns, and the channel region constituting a first column pattern is the same channel type as the adjoining channel region constituting a second column pattern. As a feature of the structure, the column pattern comprises a basic all including a P-channel region and two N-channel regions which are the same in figure and size.

Abstract: In a semiconductor device according to this invention, a first insulating film formed on only a pattern formation conductive film on a semiconductor substrate and having a reflectance which is 25% or more and periodically changes in accordance with a change in film thickness of the first insulating film is formed on the semiconductor substrate. A second insulating film having a reflectance which is 25% or more and periodically changes in accordance with a change in film thickness and having a refractive index different from that of the first insulating film is formed on only the first insulating film. A total reflectance of the first and second insulating films is less than 25%. A photosensitive film is formed on the second insulating film and exposed through a reticle to form a predetermined pattern. Etching is performed using the photosensitive film having this pattern to form a conductive pattern.

Abstract: A PMOS transistor is coupled directly to both V.sub.CC and V.sub.SS, for use in an electrostatic discharge (ESD) protection device, thereby protecting the I/O pad(s) of an integrated circuit. The direct coupling of the PMOS transistor to both voltage levels, V.sub.CC and V.sub.SS, greatly reduces the overall ESD hazard, i.e, to all four ESD conditions: 1) positive against V.sub.SS, 2) negative against V.sub.SS, 3) positive against V.sub.CC, and 4) negative against V.sub.CC, the most critical of these tests being the positive against V.sub.SS and positive against V.sub.CC.

Abstract: Signal wirings are incorporated in a semiconductor integrated circuit device for propagating a multi-bit signal from an array of pads to input buffer circuits, and either wiring gap or wiring width is changed for canceling difference in time constant due to the different wiring lengths so that the component bits of the multi-bit signal concurrently arrive at the input buffer circuits.

Abstract: Silicon MSM photodiodes sensitive to radiation in the visible to near infrared spectral range are produced by altering the absorption characteristics of crystalline Si by ion implantation. The implantation produces a defected region below the surface of the silicon with the highest concentration of defects at its base which acts to reduce the contribution of charge carriers formed below the defected layer. The charge carriers generated by the radiation in the upper regions of the defected layer are very quickly collected between biased Schottky barrier electrodes which form a metal-semiconductor-metal structure for the photodiode.

Abstract: A self-aligned through hole (5), particularly a bit line through hole to a source/drain region (2) that is self-aligned relative to the word line, is produced in neighboring word lines (3a) having a greater spacing from one another in the proximity of the source/drain region than at other locations. Narrow spacings are completely filled by surface-wide deposition of an insulating intermediate layer and subsequent, anisotropic etching, whereas insulating spacers (4") are formed in enlarged interspaces at side walls of the encapsulated word lines (3) and thereby form a self-aligned through hole.

Abstract: A method for forming field effect devices having lightly doped drain regions requires only a single dope and implant step. After patterning of the polycrystalline silicon gates, sloped sidewall spacers are formed alongside the gates. These spacers have a relatively linear slope from the top corners of the polycrystalline silicon gates to the substrate. A single implant of dopant results in heavily doped regions beyond the sidewall spacers with more lightly, and shallowly, doped regions next to the channel.

Abstract: An interconnect structure is formed having a substrate (10). A conductive layer (14) is formed overlying the substrate (10). A conductive layer (18) is formed overlying the conductive layer (14). An opening (19) is etched through the conductive layer (18), exposing a top portion of conductive layer (14), and forming a sidewall of the conductive layer (18). An selective isotropic etch procedure is used to laterally recess the sidewall of the conductive layer (18). A sidewall spacer (22) is formed adjacent the sidewall of the conductive layer (18). A conductive layer (24) is formed within opening (19) and adjacent the spacer (22) to form an interconnection between conductive layers (24 and 14). The interconnection is self-aligned, and conductive layer (18) is reliably isolated from the interconnect due to the lateral recessed sidewall of the conductive layer (18).

Abstract: A solid state imaging device of the present invention includes: a semiconductor substrate of one conductive type; a well layer made of a semiconductor of the other conductive type formed on the semiconductor substrate; a photodetecting portion made of a semiconductor of one conductive type formed in an upper portion of the well layer; a high concentration semiconductor layer made of the other conductive type formed in an upper portion of the photodetecting portion; a first region of one conductive type formed in an upper portion of the semiconductor substrate, being in contact with the well layer and positioned at least below the photodetecting portion, having higher concentration than the semiconductor substrate; and a second region of the other conductive type formed in a lower portion of the well layer, being in contact with the semiconductor substrate and positioned on the first region.

Abstract: A signal line is disposed to run parallel to electric-power supplying lines in the uppermost layer of a multi-layer wiring in an ASCI (Application-oriented Specific IC). An arbitrary cell in an I/O cell column can be interconnected to a large-size circuit element, such as a feedback resistor, formed at a corner of a semiconductor chip. Therefore, a desired function circuit block can be formed in an I/O cell corresponding to an arbitrary input/output pin so that satisfactory freedom is assured for a user who design the pattern on a printed circuit board. Since the signal line is formed by an individual conductive layer from that for the signal line and as well as it runs adjacently to the electric-power line, inductive coupling with other signal lines can significantly be reduced. As a result, a stable operation of an oscillation circuit constituted by the feedback resistor and a selected internal I/O cell can be assured.

Abstract: A MESFET which includes a semi-insulating substrate, e.g., a GaAs substrate, an insulating layer formed on a portion of the upper surface of the substrate, a first semiconductor layer formed on the upper surface of the substrate adjacent to opposite sides of the insulating layer, the first semiconductor layer having sidewalls defining a void therein, a nitride layer formed on a portion of the upper surface of the insulating layer, an oxide layer formed on the nitride layer, a second semiconductor layer formed on the sidewalls of the first semiconductor layer and in covering relationship to the void, a gate electrode formed on at least a portion of the upper surface of the second semiconductor layer, and, source and drain electrodes formed on the upper surface of the first semiconductor layer, on opposite sides of the gate electrode.

Abstract: An LED spacer assembly includes a housing having at least one first passageway which permits the insertion of an LED. The LED has leads which extend therefrom and pass through the first passageway of the housing. The housing also includes at least one second passageway which intersects the first passageway and includes an extended portion. The second passageway permits the insertion of a tool or forming die element for the purpose of holding the leads and forming a bent portion in the leads which extend into the extended portion of the second passageway. The positioning of the bent portion of the leads into the extended portion of the second passageway permits the stable retention of the LED on the housing. Additionally, by holding the leads during the bending of the same, stresses on the LED are minimized during the assembly process.

Abstract: An optoelectronic component has an LED (5) and a photodetector (6) mounted on a base (1). A housing has lenses (11, 12) for transmission of emitted/received light. A building block (13) of thin metal plate has a plurality of legs (16, 17) which, when mounting the housing on the base, are squeezed between the housing and the base and provide a mechanical locking of these two units in the desired position in relation to each other. The building element (13) has a bent-down screen portion and/or electrical screening of the semiconductor elements (5, 6) from each other. (FIG.

Abstract: A structure of a thin film transistor capable of reducing the power consumption in the waiting state and stabilizing the data holding characteristic in application of the thin film transistor as a load transistor in a memory cell in a CMOS-type SRAM is provided. A gate electrode is formed of a polycrystalline silicon film on a substrate having an insulating property. A gate insulating film is formed on the gate electrode. A polycrystalline silicon film is formed on the gate electrode with the gate insulating film interposed therebetween. Source/drain regions including a region of low concentration and a region of high concentration are formed in one and another regions of the polycrystalline silicon film separated by the gate electrode. Thus, the thin film transistor is formed. The thin film transistor is applied to p-channel MOS transistors serving as load transistors in a memory cell of a CMOS-type SRAM.

Abstract: Radiation-emitting semiconductor diodes in the form of a laser diode or in the form of an LED form important components in data-processing systems. There is a particular need for diodes which emit in the visible part of the spectrum, which have a low starting current and which can be manufactured at low cost. A radiation-emitting semiconductor diode comprising above the active layer a cladding layer and a GaAs contact layer, into which a mesa-shaped strip is etched, and provided on the upper and the lower side with a conductive layer, which forms outside the mesa-shaped strip a junction forming a barrier with a subjacent semiconductor layer, partly satisfies the aforementioned requirements.

Abstract: A contact between a heavily-doped region in the substrate and metal is made via a hole in a thick oxide layer and a polysilicon layer. The polysilicon layer is first etched to form a hole for establishing a mask for the eventual contact hole. Prior to forming the contact hole, a sidewall spacer of polysilicon is formed in the hole in the polysilicon layer. A thin oxide layer over the polysilicon layer is used for convenient end point detection during the formation of the polysilicon sidewall spacers. The sidewall spacer reduces the bore dimension of the hole in the polysilicon used for the mask for forming the contact hole. A hole is then etched in the thick oxide which is sloped and which has a bore dimension determined by the hole in the polysilicon which is reduced due to the sidewall spacer. The heavily-doped region, the contact hole, and the remaining polysilicon are coated with a barrier. The contact hole is then filled with a conductive material which also coats the barrier.

Abstract: A semiconductor integrated circuit of the laminated type having a large circuit capacity includes an upper silicon tip and a lower silicon tip as essential components and a layer of electrical insulative material is interposed between the upper silicon tip and the lower silicon tip both of which are electrically connected to each other via a number of lead wires extending therebetween. An assembly of the upper silicon tip, the electrical insulative material layer and the lower silicon tip is fixedly mounted on a base board, and the foregoing assembly is then covered with a cap.

Abstract: A phonon modulator which includes a semiconductor body having at least first and second polar semiconductor quantum wells formed therein separated by a polar semiconductor barrier. The conduction band energies of the wells and barrier are selected such that the lowest energy electronic states in the two wells are separated by an energy which is greater than the energies of optical phonons in the well and barrier materials. Respective voltages are applied to the wells which are less than the optical phonon emission threshold in the well and barrier materials to generate respective currents therein. Increasing the voltage to the first well to a level in excess of such optical phonon emission threshold causes optical phonons to be emitted from the first well to create a standing interface mode from the first well through the barrier to the second well, thereby providing a scattering mechanism for electrons in the second well and reducing the current thereof.

Abstract: A process and structure for resolving the divergent etching requirements of a relatively thick base oxide (62) and a relatively thin gate oxide (64) in a BiCMOS integrated circuit. The necessity of etching base oxide (62) is eliminated by extending nitride mask (58) over the extrinsic base region (86) so that the relatively thick base oxide (62) only covers intrinsic base region (60) and tab region (61). Base oxide (62) at tab region (61) is partially etched in the course of forming sidewall oxide filaments (78), resulting in the residual tab oxide (62'). An extrinsic base implant is performed in extrinsic base region (86) and tab region (61), with the presence of residual tab oxide (62') affecting the profile of the implant so that it is stepped. The resulting structure, after an anneal, is extrinsic base (87'), an intrinsic base (63) (formed prior to the extrinsic base implant), and an overlap region (88') common to both.

Abstract: A biasing method for and IC with enhanced reverse bias breakdown. A field plate covering the surface PN junction and extending laterally therefrom is biased to partially deplete the island under the field plate and the substrate supporting the island is biased to complete the total depletion of the island under the field plate, establishing a substantially merged vertical field at less than critical for avalanche. Because most of the charge is required to support the vertical component of the field, the rate of change in the horizontal component is small per unit of additional terminal voltage and the lateral extension of the field plate increases the breakdown voltage beyond the plane breakdown for a PN junction of a given doping profile.