Abstract: A method of forming a thin-film magnetic element, such as a TMR element or a spin valve element, on a substrate wherein at least a surface portion of a nonmagnetic metal layer is oxidized by cluster ion beam (CIB) oxidation. Specifically, the method comprises depositing a first magnetic layer on a substrate, then depositing a nonmagnetic metal layer on the first magnetic layer. At least a top surface of the nonmagnetic layer is oxidized by CIB oxidation. In one embodiment, only a top surface portion is oxidized such that a nano-oxide layer (NOL) is formed on a nonmagnetic conductive layer. In another embodiment, the nonmagnetic metal layer is oxidized throughout it's thickness such that the layer is converted to a nonmagnetic insulating film. After oxidation, a second magnetic layer is deposited on the oxidized layer.

Abstract: A method of providing fully automated processing of a Split Lot of wafers to manufacture semiconductor devices is provided. The method processes a test Lot of wafers with a production Lot. Processing of both Lots continue as a single Lot along the production processing path up to a split condition process. Processing of the production Lot is put on hold until the alternate processing or test Lot processing is completed. The two Lots are then merged and processed according to the original predefined process steps continue on both Lots.

Abstract: There is disclosed a film forming method comprising continuously discharging a solution adjusted so as to spread over a substrate by a given amount to the substrate through a discharge port disposed in a nozzle, moving the nozzle and substrate with respect to each other, and holding the supplied solution onto the substrate to form a liquid film, wherein a distance h between the discharge port of the nozzle and the substrate is set to be not less than 2 mm and to be in a range less than 5×10−5 q&ggr; (mm) given with respect to a surface tension &ggr; (N/m) of the solution, discharge speed q (m/sec) of the solution continuously discharged through the discharge port, and a constant of 5×10−5 (m·sec/N).

Abstract: A process for a trench power MOSFET comprises forming a trench on a semiconductor substrate and an oxide and nitride in the trench, etching the oxide and nitride to remain a part of them at the bottom of the trench, and subsequent procedure for the other structure of the trench power MOSFET. Due to the thick insulator formed at the bottom of the trench, the trench power MOSFET is improved by increased voltage endurance and reduced parasitic capacitance, and thereby the cell density is increased.

Abstract: Embodiments disclosed relate to wafer level burn-in of integrated circuits on a semiconductor wafer. One embodiment disclosed performs monitored burn-in on sample wafers from a manufactured lot of wafers and determines a burn-in time for the lot from results of the monitored burn-in. The burn-in on remaining wafers from the lot is then performed for the burn-in time that was determined. Another embodiment disclosed performs burn-in on wafers from a manufactured lot of wafers while monitoring in real-time the burn-in for a subset of wafers in the lot. Using fallout data from the real-time monitoring, a determination is made as to whether the burn-in time is sufficient. If the burn-in time is determined to be sufficient, then the burn-in of the lot is stopped.

Abstract: A solution for ruthenium chemical mechanical planarization containing a nitric acid and an oxidizer is disclosed. A method of forming ruthenium pattern using a polished ruthenium layer is also disclosed. The disclosed solution improves the polishing speed of ruthenium under low polishing pressure, reduces the dishing of ruthenium and decreases scratches generated in the interlayer insulating film. As a result, the disclosed solution and methods improve the techniques for device isolation and reduction of step coverage.

Abstract: Systems and methods are described for synthesis of films, coatings or layers using precursor exerted pressure containment. A method includes exerting a pressure between a first precursor layer that is coupled to a first substrate and a second precursor layer that is coupled to a second substrate; forming a composition layer; and moving the first substrate relative to the second substrate, wherein the composition layer remains coupled to the second substrate.

Abstract: The present invention presents an improved optical window deposition shield an improved optical window deposition shield for optical access to a process space in a plasma processing system through a deposition shield, wherein the design and fabrication of the optical window deposition shield advantageously provides an optically clean access to the processing plasma in the process space while sustaining substantially minimal erosion of the optical window deposition shield.

Abstract: An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.1 &mgr;m deep into the body material. The source/drain zones (140 and 142 or 160 and 162) of a p-channel IGFET (120 or 122) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed.

Abstract: A liquid crystal display device and a method of fabricating the same are disclosed in the present invention. More specifically, the method includes the steps forming a gate line on the first substrate sequentially forming a first insulating layer, an amorphous silicon layer, and a metal layer on the first substrate, patterning the metal layer to form a data line, forming a second insulating layer on the data line, patterning the second insulating layer and the amorphous silicon layer to form a passivation layer and an active layer, respectively, forming a pixel electrode at a pixel region defined by the gate and data lines, assembling the first substrate and the second substrate having a black matrix thereon, wherein the black matrix vertically overlaps at least one boundary line defined by different exposures during step-and-repeat exposure processes; and forming a liquid crystal layer between the first and second substrates.

Abstract: A method of depositing a low dielectric constant film on a substrate. In one embodiment, the method includes the steps of positioning the substrate in a deposition chamber, providing a gas mixture to the deposition chamber, in which the gas mixture is comprised of one or more cyclic organosilicon compounds, one or more aliphatic compounds and one or more oxidizing gases. The method further includes reacting the gas mixture in the presence of an electric field to form the low dielectric constant film on the semiconductor substrate. The electric field is generated using a very high frequency power having a frequency in a range of about 20 MHz to about 100 MHz.

Abstract: Methods of fabricating leadless packages are described that facilitate increased contact density. Each device area in a lead frame panel has a die attach pad and a multiplicity of conductive contacts. The contacts are carried by tie bars and the die attach pad is carried by support bars that extend from the contacts. During assembly, the lead frame panel is held in position while the die attach pad support bars are severed. Once the die attach pad support bars are severed, an adhesive tape is adhered to the bottom surface of the lead frame panel so that the die attach pad may be held in position relative to its associated contacts. After the adhesive tape has been applied, the leadless packages may be assembled in a conventional manner.

Abstract: Fluorine is implanted directly into the channel region of a PMOS transistor structure, thereby improving the noise and VT drift margin of device performance by introducing Si—F complexes at the substrate-gate oxide interface.

Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.

Abstract: The invention encompasses stacked semiconductor devices including gate stacks, wordlines, PROMs, conductive interconnecting lines, and methods for forming such structures. In one aspect, the invention includes a method of forming a conductive line comprising: a) forming a polysilicon layer; forming a silicide layer against the polysilicon layer; b) providing a conductivity-enhancing impurity within the silicide layer; and c) providing the polysilicon layer and the silicide layer into a conductive line shape. In another aspect, the invention includes a programmable-read-only-memory device comprising: a) a first dielectric layer over a substrate; b) a floating gate over the first dielectric layer; c) a second dielectric layer over the floating gate; d) a conductive line over the second dielectric layer; and e) a metal-silicide layer over the conductive line, the metal-silicide layer comprising a Group III dopant or a Group V dopant.

Abstract: Polysilicon formed over an underlying insulator may be highly selectively etched. This may permit the replacement of polysilicon gate electrode material, implementing a dual layer process or any of a variety of other applications.

Abstract: A metal oxide Semiconductor (MOS) transistor includes a gate insulating film disposed on a surface of a silicon substrate. The gate insulating film has a central portion formed on the silicon substrate and comprising a nitride insulating film, and an end portion located on each side of the central portion, the end portion being thicker than the central portion and formed of an oxide insulating film. The MOS transistor also includes a p-type gate electrode formed on the gate insulating film, sidewalls formed on both sides of the gate insulating film and the gate electrode, a pair of p-type source/drain areas formed in surface portions of the silicon substrate, and a channel area located between the pair of source/drain areas.

Abstract: Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in a charge storage part. An oxide coating film is formed on the surface of the metal interconnection at the bonding pad part, and ultraviolet rays are irradiated onto the oxide coating film for erasing of charges from the floating gate.

Abstract: A method of fabricating a semiconductor device wherein leakage current of a capacitor is reduced is provided. The method comprises steps of forming a lower electrode of the surface of a semiconductor substrate, forming a silicon nitride film over the lower electrode, applying a first heat treatment whereby the silicon nitride film is annealed in an atmosphere containing oxygen, forming a dielectric film containing alkaline earth metals over the silicon nitride film, applying a second heat treatment whereby the electric film is annealed in an atmosphere containing oxygen, and forming an upper electrode on the surface of the dielectric film.

Abstract: The invention provides robust and cost effective techniques to fabricate double-sided HSG electrodes for container capacitors. In one embodiment, this is accomplished by forming a layer of hemispherical silicon grain (HSG) polysilicon over interior surfaces of a container formed in a substrate. A barrier layer is then formed over the formed HSG polysilicon layer. Any HSG polysilicon and barrier layers formed over the substrate and around the container opening during the forming of the HSG polysilicon and barrier layers is then removed. A portion of outside surfaces of the formed HSG polysilicon is then exposed by removing the substrate, while the barrier layer is still on the interior surface of the container to prevent formation of sink holes and to prevent stringer problems during removal of the substrate. The barrier layer is then removed to expose the interior surfaces of the HSG polysilicon to form the double-sided HSG electrode.