Patents Examined by John F. Niebling
  • Multistage deposition that incorporates nitrogen via an intermediate step
    Patent number: 6828200
    Abstract: The present invention forms a nitrided dielectric layer without substantial harm to a semiconductor layer on which the dielectric layer is formed. The invention employs a multi-stage process in which dielectric sub-layers are individually nitrided before formation of a next dielectric sub-layer. The net result is a nitrided multi-layered dielectric layer comprised of a plurality of dielectric sub-layers wherein the sub-layers have been individually deposited and incorporated with nitrogen.
    Type: Grant
    Filed: January 3, 2003
    Date of Patent: December 7, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: James Joseph Chambers, Mark Visokay, Luigi Colombo
  • Method of manufacturing a trench transistor having a heavy body region
    Patent number: 6828195
    Abstract: A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.
    Type: Grant
    Filed: January 17, 2003
    Date of Patent: December 7, 2004
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Brian Sze-Ki Mo, Duc Chau, Steven Sapp, Izak Bencuya, Dean Edward Probst
  • Semiconductor member manufacturing method and semiconductor device manufacturing method
    Patent number: 6828214
    Abstract: This invention provides an SOI substrate manufacturing method using a transfer method (bonding and separation). A separation layer (12) is formed on a silicon substrate (11). A silicon layer (13), SiGe layer (14), silicon layer (15′), and insulating layer (21) are sequentially formed on the resultant structure to prepare a first substrate (10′). This first substrate (10′) is bonded to a second substrate (30). The bonded substrate stack is separated into two parts at the separation layer (12). Next, Ge in the SiGe layer (14) is diffused into the silicon layer (13) by hydrogen annealing. With this process, a strained SOI substrate having the SiGe layer on the insulating layer (21) and a strained silicon layer on the SiGe layer is obtained.
    Type: Grant
    Filed: April 2, 2002
    Date of Patent: December 7, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuya Notsu, Nobuhiko Sato
  • Semiconductor plasma processing apparatus with first and second processing state monitoring units
    Patent number: 6828165
    Abstract: A semiconductor plasma processing apparatus for processing a semiconductor wafer includes a sensor for monitoring at least one processing state of the semiconductor plasma processing apparatus, first and second processing state monitoring units coupled to the sensor, and a selector unit for selecting one of the first and second processing state monitoring units.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: December 7, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Junichi Tanaka, Hiroyuki Kitsunai, Akira Kagoshima, Daisuke Shiraishi, Hideyuki Yamamoto, Shoji Ikuhara, Toshio Masuda
  • Testing device included in the electrooptic device
    Patent number: 6828817
    Abstract: The invention provides an electrooptic device and an electronic apparatus, in which the electrical characteristics of many thin-film switching elements formed in a substrate to support an electrooptic material can be accurately inspected. The invention also provides a method for making the electrooptic device. In a TFT array substrate of a liquid crystal device, an inspection TFT is formed in one of dummy pixels disposed at the periphery of a pixel region. A pixel electrode connected to a drain region of the TFT functions as a first inspection pad. In an adjacent dummy pixel, the pixel electrode electrically connected to an extended portion of a data line functions as a second inspection pad. In another adjacent dummy pixel, the pixel electrode electrically connected to an extended portion of a scan line via a junction electrode functions as a third inspection pad.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: December 7, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Shin Fujita
  • Method of piping defect detection
    Patent number: 6825119
    Abstract: A method of piping defect detection is disclosed. First, a sample is provided. The sample has a silicon substrate, a plurality of electric devices disposed on the silicon substrate surface, a dielectric layer covering the electric devices and the substrate, and a polysilicon layer positioned on the dielectric layer, which is electrically connected to the electric devices through contact holes in the dielectric layer. A chemical mechanical polish process is performed to remove the polysilicon layer on the dielectric layer and parts of the dielectric layer. A wet etching process is then performed to delayer the dielectric layer. After that, the sample is inspected under an ultraviolet light irradiation for detecting the piping defects in the dielectric layer of the sample.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: November 30, 2004
    Assignee: Powerchip Semiconductor Corp.
    Inventor: Long-Hui Lin
  • Cell nitride nucleation on insulative layers and reduced corner leakage of container capacitors
    Patent number: 6825081
    Abstract: Methods of forming a uniform cell nitride dielectric layer over varying substrate materials such as an insulation material and a conductive or semiconductive material, methods of forming capacitors having a uniform nitride dielectric layer deposited onto varying substrate materials such as an insulation layer and overlying conductive or semiconductive electrode, and capacitors formed from such methods are provided. In one embodiment of forming a uniform cell nitride layer in a capacitor construction, a surface-modifying agent is implanted into exposed surfaces of an insulation layer of a capacitor container by low angle implantation to alter the surface properties of the insulation layer for enhanced nucleation of the depositing cell nitride material, preferably while rotating the substrate for adequate implantation of the modifying substance along the top corner portion of the container.
    Type: Grant
    Filed: July 24, 2001
    Date of Patent: November 30, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Lingyi A. Zheng
  • Flip chip package structure and flip chip device with area bump
    Patent number: 6825568
    Abstract: A structure of flip chip package with an area bump has at least a chip (also known as a die), a substrate, a plurality of first bumps (normal bumps) and at least a second bump (area bump), wherein the first bumps are electrically and mechanically connected to one of first bonding pads and the corresponding one of first contact pads. The second bump is electrically and mechanically connected to a second bonding pad and the corresponding second contact pad of the substrate, wherein the size of the second bump is larger than one of the first bumps. Because the size of the second bump is larger than one of the first bumps, the structure has much better electrical performance and performance of heat dissipation.
    Type: Grant
    Filed: September 1, 2003
    Date of Patent: November 30, 2004
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Chih-Pin Hung
  • Display apparatus
    Patent number: 6825900
    Abstract: A display apparatus which enables the display screen to be increased in size. The display apparatus includes a panel substrate operating as a display screen, plural display devices arranged in a matrix on the panel substrate, and a drive circuit substrate having a drive circuit for driving each display device. The panel substrate is subdivided into plural areas by driving wiring adapted for driving the display devices, and a plurality of the drive circuit substrates are provided in association with the respective areas.
    Type: Grant
    Filed: August 13, 2001
    Date of Patent: November 30, 2004
    Assignee: Sony Corporation
    Inventor: Toshitaka Kawashima
  • Liquid crystal display element and method of manufacturing the same
    Patent number: 6825903
    Abstract: A liquid crystal display element comprises a polarization plates, phase difference plates, a liquid crystal layer, and selectively reflective layers for reflecting part or whole of circularly polarized light in a specific direction. The products of the respective thicknesses of the polarization plate, phase difference plate, liquid crystal layer, and selectively reflective layer and the difference between an average refractive index in a direction perpendicular to each display plane and an average refractive index in a direction parallel to the display plane are set so that the absolute value of their sum total is 50 nm or less. Each selectively reflective layer is formed of a layer having positive refractive index anisotropy and a layer having negative refractive index anisotropy.
    Type: Grant
    Filed: April 24, 2001
    Date of Patent: November 30, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Ohtake, Yuzo Hisatake, Atsuko Oono
  • Semiconductor device and method for manufacturing the same
    Patent number: 6821845
    Abstract: A semiconductor device containing a dielectric capacitor having an excellent step coverage for a device structure of high aspect ratio corresponding to high integration degree, as well as a manufacturing method therefor are provided. A dielectric capacitor of high integration degree is manufactured by forming a bottom electrode 46 and a top-electrode 48 comprising a homogeneous thin Ru film with 100% step coverage while putting a dielectric 47 therebetween on substrates 44, 45 having a three-dimensional structure with an aspect ratio of 3 or more by a MOCVD process using a cyclopentadienyl complex within a temperature range from 180° C. or higher to 250° C. or lower.
    Type: Grant
    Filed: April 5, 2001
    Date of Patent: November 23, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Toshihide Nabatame, Takaaki Suzuki, Tetsuo Fujiwara, Kazutoshi Higashiyama
  • Method for manufacturing semiconductor device, substrate treatment method, and semiconductor manufacturing apparatus
    Patent number: 6821871
    Abstract: It is an object of the present invention to make it easy to diffuse phosphorus into a silicon film and allow the phosphorus diffusion concentration to be easily controlled by varying the timing at which the dopant gas is allowed to flow. A silicon wafer 10 on whose surface an amorphous silicon film 12 has been formed is placed in a diffusion furnace. After this, phosphine (PH3) or a mixed gas containing phosphine is allowed to begin flowing over the wafer 15 and the phosphorus is diffused into the silicon film 12 before the amorphous silicon film 12 crystallizes and changes into a polysilicon film.
    Type: Grant
    Filed: June 13, 2001
    Date of Patent: November 23, 2004
    Assignees: Hitachi Kokusai Electric Inc., Hitachi, Ltd.
    Inventors: Hisashi Nomura, Yushin Takasawa, Hajime Karasawa, Yoshinori Imai, Tadanori Yoshida, Kenichi Yamaguchi
  • Infrared thermopile detector system for semiconductor process monitoring and control
    Patent number: 6821795
    Abstract: A thermopile-based detector for monitoring and/or controlling semiconductor processes, and a method of monitoring and/or controlling semiconductor processes using thermopile-based sensing of conditions in and/or affecting such processes.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: November 23, 2004
    Assignee: Advanced Technology Materials, Inc.
    Inventor: Jose Arno
  • Method of manufacturing a semiconductor device
    Patent number: 6821827
    Abstract: The present invention relates to a method of manufacturing a semiconductor device having an excellent gettering effect. In this method, when phosphorus is added to a poly-Si film, which has been crystallized by the addition of a metal, to subject the resultant poly-Si film to the heat treatment to carry out gettering therefor, the device is performed for the shape of the island-like insulating film on the poly-Si film which is employed when implanting phosphorus. Thereby, the area of the boundary surface between the region to which phosphorus has been added and the region to which no phosphorus has been added is increased to enhance gettering efficiency.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: November 23, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Osamu Nakamura, Manabu Katsumura, Shunpei Yamazaki
  • Gas distribution system for cyclical layer deposition
    Patent number: 6821563
    Abstract: Embodiments of the invention are generally directed to a cyclical layer deposition system, which includes a processing chamber, at least one load lock chamber connected to the processing chamber, a plurality of gas ports disposed on the processing chamber. The gas ports are configured to transmit one or more gas streams into the processing chamber. The system further includes a plurality of vacuum ports disposed on the processing chamber between the gas ports. The vacuum ports are configured to transmit the gas streams out of the processing chamber.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: November 23, 2004
    Assignee: Applied Materials, Inc.
    Inventor: Joseph Yudovsky
  • Semiconductor device including a field effect transistor and a passive capacitor having reduced leakage current and an improved capacitance per unit area
    Patent number: 6821840
    Abstract: A semiconductor device comprises a field effect transistor and a passive capacitor, wherein the dielectric layer of the capacitor is comprised of a high-k material, whereas the gate insulation layer of the field effect transistor is formed of an ultra thin oxide layer or oxynitride layer so as to provide for superior carrier mobility at the interface between the gate insulation layer and the underlying channel region. Since carrier mobility in the capacitor is not of great importance, the high-k material allows the provision of high capacitance per unit area while featuring a thickness sufficient to effectively reduce leakage current.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: November 23, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Karsten Wieczorek, Gert Burbach, Thomas Feudel
  • Method of using beam homogenizer and laser irradiation apparatus
    Patent number: 6818568
    Abstract: There is provided a beam homogenizer which can unify the energy distribution of a linear laser beam in a longitudinal direction. In the beam homogenizer including cylindrical lens groups for dividing a beam, and a cylindrical lens and a cylindrical lens group for condensing the divided beams, the phases, in the longitudinal direction, of linear beams passing through individual cylindrical lenses of the cylindrical lens group for condensing the divided beams are shifted, and then, the beams are synthesized, so that the intensity of interference fringes of the linear beam on a surface to be irradiated is made uniform.
    Type: Grant
    Filed: April 16, 2002
    Date of Patent: November 16, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Koichiro Tanaka
  • Process and apparatus for removal of photoresist from semiconductor wafers using spray nozzles
    Patent number: 6818563
    Abstract: A process for removing photoresist from semiconductor wafers is disclosed wherein at least one semiconductor wafer having at least one layer of photoresist is positioned in a process tank; ozone gas is provided to said process tank; and said semiconductor wafer is spayed with a mixture of ozone and deionized water via at least one nozzle. The temperature during the process is maintained at or above ambient temperature. The ozone gas supplied to the tank is preferably under pressure within said process tank and the nozzles preferably spray the mixture of deionized water and ozone at a nozzle pressure between 5 and 10 atmospheres. In another embodiment, the invention is an apparatus for carrying out the process.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: November 16, 2004
    Assignee: Akrion LLC
    Inventors: Richard Novak, Ismail Kashkoush, Gim-Syang Chen, Dennis Nemeth
  • Reciprocating gas valve for pulsing a gas
    Patent number: 6818094
    Abstract: A gas valve for pulsing a gas comprises a housing assembly having at least one inlet port, an outlet port, and a selector plate mounted within the housing assembly and comprising at least one timing slot, wherein reciprocation motion of the selector plate periodically couples at least one inlet port to the outlet port through the timing slot.
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: November 16, 2004
    Assignee: Applied Materials, Inc.
    Inventor: Joseph Yudovsky
  • Method of forming a gate electrode in a semiconductor device
    Patent number: 6818506
    Abstract: The present invention relates to a method of forming a gate electrode in a semiconductor device. Upon deposition processes for forming doped and undoped polysilicon films constituting a gate electrode, the deposition processes are performed at different temperatures. Thus, generation of an alien substance on the surface of the doped polysilicon film can be prohibited. As a result, the gate electrode having no defect can be implemented.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: November 16, 2004
    Assignee: Hynix Semiconductor Inc.
    Inventors: Kwang Chul Joo, Cha Deok Dong