Abstract: A method of making a lead frame and a partially patterned lead frame package with near-chip scale packaging (CSP) lead-counts is accomplished by performing a major portion of the manufacturing process steps with a partially patterned strip of metal formed into a web-like lead frame on one side, so that the web-like lead frame, which is solid and flat on the other side is also rigid mechanically and robust thermally to perform without distortion or deformation during the chip-attach and wire bond processes, both at the chip level and the package level. The bottom side of the metal lead frame is patterned to isolate the chip-pad and the wire bond contacts only after the front side, including the chip and wires, is hermetically sealed with an encapsulant. The resultant package being electrically isolated enables strip testing and reliable singulation without having to cut into any additional metal.

Abstract: A gas supplying apparatus of a system for fabricating semiconductor devices is tested for clogs. The gas supplying apparatus includes a carrier gas supplying device for supplying at least one carrier gas, and a plurality of reactive gas supplying devices connected in parallel to the carrier gas supplying device. The reactive gas supplying devices gasify the reactive gas carried by the carrier gas. A wafer, on which a desired layer is to be formed, is situated in a process chamber into which the reactive gas is supplied from the reactive gas supplying devices. The gas supplying apparatus also includes pressure detecing devices for detecting the pressure of the carrier gas near each of the reactive gas supplying devices. The carrier gas is supplied under a predetermined pressure to the reactive gas supplying devices. The reactive gas supplying device to be tested for clogs is rendered operational while the other reactive gas supplying devices are shut down.

Abstract: Embodiments of methods of fabricating protected contact plugs include forming an electrically insulating layer having a contact hole therein, on a semiconductor substrate and then forming an electrically conductive lower barrier layer that lines at least an upper portion of a sidewall of the contact hole. This lower barrier layer may comprise titanium nitride (TiN). A step is also performed to form an electrically conductive contact plug that extends in the contact hole, is electrically coupled to the lower barrier layer and protrudes above the electrically insulating layer. The contact plug may comprise tungsten (W). An electrically conductive upper barrier layer is then formed that extends on a protruded upper surface of the contact plug and on a surface of the lower barrier layer.

Abstract: A high voltage MOSFET device (100) has an nwell region (113) with a p-top layer (108) of opposite conductivity formed to enhance device characteristics. The p-top layer is implanted through a thin gate oxide, and is being diffused into the silicon later in the process using the source/drain anneal process. There is no field oxide grown on the top of the extended drain region, except two islands of field oxide close to the source and drain diffusion regions. This eliminates any possibility of p-top to be consumed by the field oxide, and allows to have a shallow p-top with very controlled and predictable p-top for achieving low on-resistance with maintaining desired breakdown voltage.

Abstract: The method provides a temperature controlled environment for processing semiconductor wafers at elevated temperatures. A hot wall process chamber is used for the process steps. The process chamber includes three zones with independent temperature control capabilities. The method may include rotating the wafers in addition to providing a gas flow velocity gradient above the wafer for improved temperature and processing uniformity results.

Abstract: An improved furnace system and method is provided to substantially minimize, if not eliminate, ambient air from entering a heated chamber of the furnace system during a critical processing step. The furnace system can be used in, for example, an oxidation step where ambient air containing oxygen is prevented from entering an atmospheric pressure tube by essentially purging potential leak areas with an inert gas, such as nitrogen, at the critical moment during temperature ramp up and ramp down, and prior to temperature stabilization and the introduction of an oxidizing gas. If oxygen is not present within the tube, then a tungsten sidewall surface of a gate conductor, for example, will not inadvertently oxidize at the critical pre- and post-oxidation moments. However, if steam is present where hydrogen is available with oxygen, the underlying polysilicon sidewall surface will selectively oxidize instead of the overlying tungsten.

Abstract: A method of preventing formation of titanium oxide within a semiconductor device structure during a high temperature treatment of the device structure includes forming a passivation layer to preclude formation of titanium oxide at a titanium/oxide interface of a semiconductor device structure. The method includes providing a substrate assembly including at least an oxide region and forming a layer of titanium over a surface of the oxide region. The oxide region surface is treated with a plasma comprising nitrogen prior to forming the titanium layer so as to form a passivation layer upon which the titanium layer is formed. A thermal treatment is performed on the substrate assembly with the passivation layer substantially inhibiting diffusion of oxygen from the oxide layer during the thermal treatment of the substrate assembly. Generally, the passivation layer comprises SixOyNz.

Abstract: A method of manufacturing a semiconductor device includes forming a silicon nitride layer on a semiconductor substrate on which a predetermined pattern is formed. The silicon nitride layer includes a plurality of bonds formed between silicon and nitrogen. A portion of the bonds formed between silicon and nitrogen is broken to form at least one free bonding site on a surface of the silicon nitride layer. A silane compound and a flow fill method are used to form a silicon oxide layer on the silicon nitride layer.

Abstract: A method of planarizing wafers using shallow trench isolation is described. The method uses a very hard polishing pad and chemical mechanical polishing with no additional etching required. Trenches are formed in a substrate and filled with a trench dielectric, such as silicon dioxide deposited using high density plasma chemical vapor deposition. A layer of resist is then formed on the layer of trench dielectric. The wafer is then planarized using chemical mechanical polishing and a polishing pad having a hardness of at least Shore “D” 52. The hard polishing pad avoids scratch marks on the trench dielectric, the substrate surface, or any other materials deposited on the substrate surface.

Abstract: Disclosed is a method for detecting electrical defects on test structures of a semiconductor die. The test structures includes a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures. The test structures each has a portion located partially within a scan area. The portion of the test structures located within the scan area is scanned to obtain voltage contrast images of the test structures' portions. In a multi-pixel processor, the obtained voltage contrast images are analyzed to determine whether there are defects present within the test structures. In a preferred embodiment, the multi-pixel processor operates with pixel resolution sizes in a range of about 25 nm to 200 nm. In another aspect, the processor operates with a pixel size nominally equivalent to two times a width of the test structure's line width to maximize throughput at optimal signal to noise sensitivity.

Abstract: A reduction of the junction electric field intensity is accomplished in the semiconductor regions for the sources and drains of field effects transistors. For this purpose, a structure is provided where the gate electrodes 9 of the MIS.FETQs for memory cell selection of a DRAM are buried within the trenches 7a and 7b created in the semiconductor substrate 1. The bottom corners within the trench 7b are rounded so as to have a radius of curvature in accordance with the sub-threshold coefficient of the MIS.FETQs for memory cell selection. In addition, the gate insulating film 8 within the trench 7b is made to have a laminated structure of a thermal oxide film and a CVD film.

Abstract: A laser treatment apparatus is provided which is capable of irradiating a laser beam to the position where a TFT is to be formed over the entire surface of a large substrate to achieve the crystallization, thereby forming a crystalline semiconductor film having a large grain diameter with high throughput. A laser treatment apparatus includes a laser oscillation device, a lens for converging a laser beam, such as a collimator lens or a cylindrical lens, a fixed mirror for altering an optical path for a laser beam, a first movable mirror for radially scanning a laser beam in a two-dimensional direction, and an f&thgr; lens for keeping a scanning speed constant in the case of laser beam scanning. These structural components are collectively regarded as one optical system. A laser treatment apparatus shown in FIG. 1 has a structure in which five such optical systems are placed.

Abstract: A product wafer processed by a semiconductor manufacturing apparatus is transferred to a check apparatus for checking, and a result thereof is sent to a host computer. A product wafer determined as being failed as a result of the checking is transported into an empty carrier by a built-in type wafer transport apparatus under the instruction of the host computer. The carrier in which the product wafer determined as being failed is accommodated is regarded as a rework lot by the host computer. Based on manufacturing standard information for rework held by the host computer, rework processing is performed through a wafer manufacturing operation. Therefore, such a semiconductor device manufacturing line results in that the carrier accommodating the product wafer is transferred and handled smoothly.

Abstract: A flat panel fluorescent lamp includes first and second glass substrates coupled with each other, at least one discharge path formed in the second glass substrate, and at least one pair of electrodes formed at the discharge path.

Abstract: The specification describes a pattern transfer technique for forming patterns of thin films of high resolution over large areas. It involves forming a pattern layer on a transfer substrate, patterning the pattern layer while on the transfer substrate, then contacting the transfer substrate with the receiving substrate. The surface of the receiving substrate is treated to activate the surface thereby improving adhesion of the transfer pattern to the receiving substrate. The activation treatment involves forming a layer of metal particles on the surface of the receiving substrate. The pattern layer is preferably of the same metal, or a similar metal or alloy, and is transferred from the transfer substrate to the receiving substrate by metallurgical bonding. The method of the invention is particularly useful for printing metal conductor patterns (metalization), and device features, on flexible polymer substrates in, for example, thin film transistor (TFT) technology.

Abstract: The present invention provides an EDMOS (extended drain MOS) device having a lattice type drift region and a method of manufacturing the same. In the case of n channel EDMOS(nEDMOS), the drift region has a lattice structure in which an n lattice having a high concentration and a p lattice having a low concentration are alternately arranged. As a drain voltage is applied, a depletion layer is abruptly extended by a pn junction of the n lattice and the p lattice, so that the entire drift region is easily depleted. Therefore, a breakdown voltage of the device is increased, and an on resistance of the device is decreased due to the n lattice with high concentration.

Abstract: Methods for fabricating a layer of oxide on a silicon carbide layer are provided by forming the oxide layer on the silicon carbide layer by oxidizing the silicon carbide layer in an N2O environment. A predetermined temperature profile and/or a predetermined flow rate profile of N2O are provided during the oxidation. The predetermined temperature profile and/or predetermined flow rate profile may be constant or variable and may include ramps to steady state conditions. The predetermined temperature profile and/or the predetermined flow rate profile are selected so as to reduce interface states of the oxide/silicon carbide interface with energies near the conduction band of SiC.

Abstract: A method of fabricating a gate structure of a field effect transistor comprising processes of forming an &agr;-carbon mask and plasma etching a gate electrode and a gate dielectric using the &agr;-carbon mask. In one embodiment, the gate dielectric comprises hafnium dioxide.

Abstract: A pan/tilt camera system includes a sensor spaced from a rotational shaft of a pan/tilt camera, a detected piece rotated with the rotational shaft so as to correspond to the sensor, an origin setting unit rotating the rotational shaft in a first direction upon turn-on of a power and thereafter in a second direction opposite to the first direction so that the sensor detects a rear end of the detected piece for setting an origin, a pulse counter applying a predetermined number of pulses to the motor after set of the origin so that the rotational shaft is continuously rotated in the second direction and counting pulses applied to the motor until a front end of the detected piece with respect to the rotation direction of the detected piece is detected, and a backlash calculating unit comparing a count of the pulse counter with the predetermined number of pulses applied to the motor thereby to calculate an amount of backlash of the drive mechanism.

Abstract: Chips C which have already been diced are attached to a ring frame F using an adhesive sheet, and a protective sheet S1 is attached to a circuit pattern surface of the chips C. The chips C, along with a ring frame F, are held in place on a table 27 of a protective sheet peeling apparatus 20. A supply portion for an adhesive tape T is disposed in the vicinity of a table 24, and the supplied adhesive tape T is attached to the protective sheet S1. When the protective sheet S1 is peeled from the circuit pattern surface, peeling starts from corner portions of the chips C or opposing corner positions by pulling the adhesive tape T.