Abstract: A method and system for reclaiming virgin test wafers by polishing a very thin layer from the wafer surface, applying a low down force between the wafer and the pad, with a dilute, low basic slurry. By polishing only a few hundred Angstroms of silicon from the wafer surface, a virgin test wafer may be repeatedly reclaimed and reused for periodic defect monitoring.

Abstract: A test structure pattern includes a first comb, a second comb, and a serpentine line. The first comb includes a first set of tines of the same orientation. The second comb includes a second set of tines of the same orientation that are interdigitated with the first set of tines. The serpentine line runs between the interdigitated tines of the first metal comb and the second metal comb. The test structure pattern forms a first metal comb, a second metal comb, and a serpentine metal line on a die. Print quality and resolution is tested by checking for electrical continuity in the serpentine metal line and bridging between the serpentine metal line and one of the first metal comb and the second metal comb.

Abstract: Upon formation of semiconductor micro patterns, an interlayer alignment error occurs due to asymmetry of each alignment mark. Prior to alignment of a mask with a wafer, the asymmetry of each alignment mark is measured according to the principle of a scatterometry, and the alignment is performed in consideration of the result of measurement to execute exposure. Thus, high-accuracy alignment can be carried out without sacrificing throughput, and the performance of a semiconductor device is improved. Further, manufacturing yields can be enhanced and a reduction in cost can be realized.

Abstract: A nondestructive inspection device (or method) is basically configured such that a laser beam (1300 nm) is irradiated on a surface (or back) of a semiconductor device chip to scan. Due to irradiation of the laser beam, a defect position is heated to cause a thermoelectromotive current, which induces a magnetic field. A magnetic field detector such as SQUID detects a strength of the magnetic field, based on which a scan magnetic field image is produced. A display device superimposes the scan magnetic field image on a scan laser microphotograph on a screen, so it is possible to perform defect inspection on the semiconductor device chip. Incidentally, a semiconductor device wafer is constructed to include a thermoelectromotive force generator and its wires, which are electrically connected to first-layer wires. By irradiation of the laser beam on the thermoelectromotive force generator, it is possible to detect a short-circuit defect, which lies between the first-layer wires.

Abstract: An unsingulated semiconductor wafer is provided. Electrical interconnect elements are formed on the unsingulated wafer such that the interconnect elements are electrically connected to terminals of the semiconductor dice composing the wafer. At least a portion of the interconnect elements extend beyond the boundaries of the dice into the scribe streets separating the individual dice. Thereafter, the wafer is singulated into individual dice.

Abstract: A preferred embodiment includes a method for monitoring the performance of a filter positioned in an airstream in a semiconductor processing system. The method includes sampling the airstream at a location upstream of the filter to detect the molecular contaminants present in the airstream; identifying a target species of the contaminants upstream; selecting a non-polluting species of a contaminant having a concentration greater than a concentration of the target species; measuring the non-polluting species in the airstream at a plurality of locations; and determining the performance of the filter with respect to the target species from measurements of the non-polluting species. The plurality of locations includes a location downstream of the filter and at a location within the filter. Further, the method for monitoring includes generating a numerical representation of a chromatogram of the airstream sampled at a location upstream of the filter.

Abstract: An insulation film is formed on a semiconductor substrate by a method including the steps of: (i) introducing a source gas comprising a compound composed of at least Si, C, and H into a chamber; (ii) introducing in pulses an oxidizing gas into the chamber, wherein the source gas and the oxidizing gas form a reaction gas; and (iii) forming an insulation film on a semiconductor substrate by plasma treatment of the reaction gas. The plasma treatment may be plasma CVD processing.

Abstract: Disclosed is a semiconductor manufacturing apparatus which includes a chamber having an environment-controlled inside space, a stage disposed in the inside space of the chamber and for holding a substrate to perform a predetermined process to the substrate, a temporary storage for temporarily storing one or more substrates in a local environment being independent from the chamber inside, a robot for conveying a substrate between the stage and the temporary storage, and a controller for controlling the robot so that the substrate is stored into the temporary storage when the environment control of the chamber inside space is suspended.

Abstract: An n-type MOSFET (NMOS) is implemented on a substrate having an epitaxial layer of strained silicon formed on a layer of silicon germanium. The MOSFET includes first halo regions formed in the strained silicon layer that extent toward the channel region beyond the ends of shallow source and drain extensions. Second halo regions formed in the underlying silicon germanium layer extend toward the channel region beyond the ends of the shallow source and drain extensions and extend deeper into the silicon germanium layer than the shallow source and drain extensions. The p-type dopant of the first and second halo regions slows the high rate of diffusion of the n-type dopant of the shallow source and drain extensions through the silicon germanium toward the channel region. By counteracting the increased diffusion rate of the n-type dopant in this manner, the shallow source and drain extension profiles are maintained and the risk of degradation by short channel effects is reduced.

Abstract: A process for forming active transistors for a semiconductor memory device by the steps of: forming transistor gates having generally vertical sidewalls in a memory array section and in periphery section; implanting a first type of conductive dopants into exposed silicon defined as active area regions of the transistor gates; forming temporary oxide spacers on the generally vertical sidewalls of the transistor gates; after the step of forming temporary spacers, implanting a second type of conductive dopants into the exposed silicon regions to form source/drain regions of the active transistors; after the step of implanting a second type of conductive dopants, growing an epitaxial silicon over exposed silicon regions; removing the temporary oxide spacers; and forming permanent nitride spacers on the generally vertical sidewalls of the transistor gates.

Abstract: A method of manufacturing an organic electroluminescent device has the steps of forming a first electrode on a substrate, preparing a solution containing a hole transport organic material, an electron transport organic material and a luminescent organic material, followed by spraying the solution onto the first electrode by using a pressurized gas so as to form an organic thin film layer, and forming a second electrode on the organic thin film layer.

Abstract: A load port of a semiconductor manufacturing apparatus includes a plurality of kinematic coupling pins and a plurality of sensors integrated with the pins. The contacts of the sensors have upper portions that protrude from the pins. Thus, when a cassette is place on the load port, the sensors can reliably sense whether the cassette is resting properly and/or can determine whether the cassette contains wafers. Once such determinations are made in the positive, a command signal is issued that serves to load the wafers into a chamber of the manufacturing apparatus.

Abstract: A method and an apparatus for performing cascade control of processing of semiconductor wafers. A first semiconductor wafer for processing is received. A second semiconductor wafer for processing is received. A cascade processing operation upon the first and the second semiconductor wafers is performed, wherein the cascade processing operation comprises acquiring pre-process metrology data related to the second semiconductor wafer during at least a portion of a time period wherein the first semiconductor wafer is being processed.

Abstract: A manufacturing method of a semiconductor device to perform processing, including pre-processing and post-processing, on a semiconductor substrate, a characteristic of the processed semiconductor substrate is inspected, whether the semiconductor substrate complies with a predetermined standard is judged, and a semiconductor substrate not complying with the standard is re-processed so that the semiconductor substrate complies with the standard.

Abstract: A process to deposit a thin film by chemical vapor deposition includes evacuating a chamber of gases; exposing a device to a gaseous first reactant, wherein the first reactant deposits on the device to form the thin film having a plurality of monolayers in thickness; evacuating the chamber of gases; exposing the device, coated with the first reactant, to a gaseous second reactant under a plasma treatment, wherein the thin film is treated by the first reactant; and repeating the previous steps.

Abstract: An improved method for pick and place equipment operation is provided by an improved method for identifying the reference die on a wafer. A recording of good die, partial die, mirror die, and partial mirror die information about the neighboring dies about the reference die is formed by recording step is performed by starting at the reference die and moving clockwise about the reference die one die at a time to form a stored neighborhood matrix. Searching and identifying the reference die on a wafer includes aligning the wafer table with a wafer thereon at the reference die location coordinates determined by the recording step and starting at this location moving the wafer table one die at a time about the aligned reference die recording the neighboring die or partial die as full good die, partial die, mirror die, or partial mirror die and comparing to the information about dies or partial dies neighboring said reference die to identify the reference die.

Abstract: A method for preventing burnt fuse pads from further electrical connection suitable before the formation of bumps on the wafer. A dielectric layer is formed over the active surface of the wafer covering the bump pads and the fuse pads of the wafer, wherein a central region of the fuse pads is burnt to form a gap which allows the material of the dielectric layer to fill up the gap. Afterwards, either a part of the dielectric layer is removed and the part of the dielectric layer covering the fuse pads remainsor a part of the dielectric layer covering the bump pads is removed. Then, an under ball metallurgy layer is formed on the bump pads of the wafer so that the material of the under ball metallurgy layer does not cover the two sides of the fuse pad at the same time, or fill into the gap. As a result, the electrical isolation still remains.

Abstract: Deep reactive ion etching creates a single mask MEMS structure 20-50 &eegr;m deep on the top surface of a wafer. Thereafter, a bottom surface etch cooperates with trenches formed in the MEMS structure to provide through trenches which release large area structures of arbitrary shape and having a thickness up to that of the wafer. The released structure is supported in the wafer by MEMS support beams and motion is detected and affected by MEMS sensors and actuators, respectively.

Abstract: The invention includes a semiconductor construction having a pair of channel regions that have sub-regions doped with indium and surrounded by boron. A pair of transistor constructions are located over the channel regions and are separated by an isolation region. The transistors have gates that are wider than the underlying sub-regions. The invention also includes a semiconductor construction that has transistor constructions with insulative spacers along gate sidewalls. Each transistor construction is between a pair source/drain regions that extend beneath the spacers. A source/drain extension extends the source/drain region farther beneath the transistor constructions on only one side of each of the transistor constructions. The invention also includes methods of forming semiconductor constructions.

Abstract: A method for making a semiconductor device having a pattern of highly doped regions located some distance apart in a semiconductor substrate and regions of low doping located between the highly doped regions. A diffusion barrier material is applied to the semiconductor substrate at the location of the regions of low doping by imprinting with the barrier material in the pattern of the regions of low doping. The doping material is applied after or before imprinting with barrier material so that the highly doped regions are formed essentially between the barrier material in the substrate.