Abstract: A method for improving the channel doping profile of deep-submicron field effect transistors and MOSFETs. The method involves a highly localized halo implant formed in the channel region but not in the source/drain junction. The halo implant is performed through a gap formed by removal of a temporary spacer. The MOSFET is then further completed.

Abstract: A technique in accordance with the invention includes obtaining a semiconductor structure that has a metal disposed thereon. At least a portion of the metal is etched using an etching fluid while sonic energy is applied to the etching fluid.

Abstract: An organic thin film transistor includes: an organic thin film which includes a compound represented by the following general formula [A]: X—[—N Ar1Ar2]n  [A] where each of Ar1 and Ar2 is selected independently from unsubstituted or substituted aromatic hydrocarbon groups having 6 to 20 carbon atoms and from unsubstituted or substituted aromatic heterocyclic groups having 6 to 20 carbon atoms; and X is selected from unsubstituted or substituted condensed aromatic hydrocarbon groups having 6 to 34 carbon atoms, and the condensed aromatic hydrocarbon groups are monovalent, divalent, trivalent or tetravalent groups; and n is the natural number in the range of 1-4.

Abstract: Micro-miniaturized semiconductor devices having transistors with abrupt high concentration shallow source/drain extensions are fabricated by sequentially forming deep source/drain regions, pre-amorphizing intended shallow source/drain extension regions, ion implanting impurities into the pre-amorphized regions and then laser thermal annealing to crystallize the pre-amorphized regions and to activate the source/drain extensions. Embodiments include forming the deep source/drain regions using removable sidewall spacers on the gate electrode, removing the sidewall spacers, forming the ion implanted pre-amorphized source/drain exension implants, forming laser transparent oxide sidewall spacers on the gate electrode and laser thermal annealing through the oxide laser transparent sidewall spacers to selectively activate the source/drain extensions.

Abstract: A method of manufacturing an integrated circuit includes providing an amorphous semiconductor material including germanium, annealing the amorphous semiconductor material, and doping to form a source location and a drain location. The semiconductor material containing germanium can increase the charge mobility associated with the transistor.

Abstract: A method and associated apparatus for creating a defect knowledge library containing case study information of wafer defects on semiconductor wafers. The method comprises creating a database entry that contains a case study of a specific defect including defect information that comprises one or more defect images and storing the database entry for subsequent access. The database entries are stored on a server and are accessible by a plurality of clients.

Abstract: A method of making a semiconductor device includes thickening source and drain regions. After a field effect device having a source region, a drain region, and a gate, is formed, a layer of semiconductor material is deposited on the device by a directional deposition method, such as collimated sputtering. Then the semiconductor material is selectively removed from side walls on either side of the gate, such as by isotropic back etching, leaving thickened semiconductor material in the source and drain regions, and on the gate.

Abstract: In a method of manufacturing a semiconductor device comprising a semiconductor body 1 which is provided at a surface 2 with a transistor comprising a gate structure 21, a patterned layer 10 is applied defining the area of the gate structure 21. Subsequently, a dielectric layer 18 is applied in such a way, that the thickness of the dielectric layer 18 next to the patterned layer 10 is substantially equally large or larger than the height of the patterned layer 10, which dielectric layer 18 is removed over part of its thickness until the patterned layer 10 is exposed. Then, the patterned layer 10 is subjected to a material removing treatment, thereby forming a recess 19 in the dielectric layer 18, and a contact window 28,29 is provided in the dielectric layer.

Abstract: The invention includes reactive gaseous deposition precursor feed apparatus and chemical vapor deposition methods. In one implementation, a reactive gaseous deposition precursor feed apparatus includes a gas passageway having an inlet and an outlet. A variable volume accumulator reservoir is joined in fluid communication with the gas passageway. In one implementation, a chemical vapor deposition method includes positioning a semiconductor substrate within a deposition chamber. A first deposition precursor is fed to an inlet of a variable volume accumulator reservoir. With the first deposition precursor therein, volume of the variable volume accumulator reservoir is decreased effective to expel first deposition precursor therefrom into the chamber under conditions effective to deposit a layer on the substrate.

Abstract: There is provided a semiconductor device in which improvement of drive capacity and miniaturization are made. A P-type transistor is composed of a surface channel type transistor so that a channel length is easily reduced. Thus, improvement of drive capacity and miniaturization are promoted. Further, since a gate insulating film is nitrided, reliability of the gate insulating film is improved and passing of boron contained in a p-type polycrystalline silicon gate electrode toward a channel region can be prevented. A step of forming the gate insulating film, a step of nitriding the gate insulating film, a step of performing thermal treatment using an inert gas, a step of forming a gate electrode on the gate insulating film, and a step of introducing a p-type impurity into the gate electrode are performed. Thus, a surface channel P-type transistor and a buried channel N-type transistor are constructed.

Abstract: A semiconductor integrated circuit is provided in which a change in timing of a circuit or variation in a driving ability do not occur even if the potential of a support substrate is fixed.

Abstract: A method of fabricating a polysilicon film by an excimer laser annealing process is introduced. First, an amorphous silicon film is deposited on a substrate composed of glass. The amorphous silicon film includes a first region, which is located in the center, with a first thickness, and a second region, which is located in the periphery, with a slant sidewall. The thickness of the amorphous silicon film is measured so as to obtain the profile of the sidewall in the second region. According to the profile of the sidewall, a pre-cursor region is determined for performing an excimer laser annealing process wherein a second thickness in the boundary of the pre-curser regionis smaller than the first thickness so as to increase area of produced polysilicon film.

Abstract: In one embodiment, the present invention relates to a method of forming a shallow trench, involving the steps of providing a semiconductor substrate comprising a barrier oxide layer over at the semiconductor substrate and a nitride layer over the barrier oxide layer; depositing an ultra-thin photoresist over the nitride layer, the ultra-thin photoresist having a thickness of about 2,000 Å or less; patterning the ultra-thin photoresist to expose a portion of the nitride layer and to define a pattern for the shallow trench; etching the exposed portion of the nitride layer with an etchant having a nitride:photoresist selectivity of at least about 10:1 to expose a portion of the barrier oxide layer; etching the exposed portion of the barrier oxide layer to expose a portion of the semiconductor substrate; and etching the exposed portion of the semiconductor substrate to provide the shallow trench.

Abstract: A method and an apparatus for the determination of a process flow based upon fault detection. A process step upon a workpiece is performed. Fault detection analysis based upon the process step performed upon the workpiece is performed. A workpiece routing process is performed based upon the fault detection analysis. The wafer routing process includes using a controller to perform one or a rework process routing, a non-standard process routing, a fault verification process routing, a normal process routing, or a termination process routing, based upon the fault detection analysis.

Abstract: A structure and a method are disclosed of an enhanced T-gate for modulation doped field effect transistors (MODFETs). The enhanced T-gate has insulator spacer layers sandwiching the neck portion of the T-gate. The spacer layers are thinner than the T-bar portion overhang. The insulating layer provides mechanical support and protects the vulnerable neck portion of the T-gate from chemical attack during subsequent device processing, making the T-gate structure highly scalable and improving yield. The use of thin conformal low dielectric constant insulating layers ensures a low parasitic gate capacitance, and reduces the risk of shorting gate and source metallurgy when source-to-gate spacings are reduced to smaller dimensions.

Abstract: In a method of forming a contact, a liner reactive ion etch is affected on a substrate to remove silicon nitride and silicon oxide. An oxygen plasma ex-situ clean, a Huang AB clean, and a dilute hydrofluric acid (DHF) clean are affected. Amorphous silicon is deposited and an anneal is performed to regrow and recrystallize amorphous silicon.

Abstract: A process for forming an organic semiconducting layer having molecular alignment. First, a photoalignment organic layer is formed on a substrate or A dielectric layer. Next, the photoalignment organic layer is irradiated by polarized light through a mask, such that the photoalignment organic layer becomes an orientation layer having molecular alignment. Finally, an organic semiconducting layer is formed on the orientation layer, such that the organic semiconducting layer aligns according to the alignment of the orientation layer to exhibit molecular alignment. The present invention can form an organic semiconducting layer with different molecular alignments in different regions over the same substrate by means of polarized light exposure through a mask.

Abstract: A method of forming a deep trench DRAM cell on a semiconductor substrate has steps of: forming a deep trench capacitor in the semiconductor substrate; using silicon-on-insulator (SOI) technology to form a silicon layer on the deep trench capacitor; and forming a vertical transistor on the silicon layer over the deep trench capacitor, wherein the vertical transistor is electrically connected to the deep trench capacitor.

Abstract: A reflective liquid crystal device includes a reflecting electrode (14) provided on the liquid crystal side of a first substrate (10), and a first retardation plate (106), a second retardation plate (116) and a polarizer (105), which are provided on the side of a second substrate (20), which is opposite to the liquid crystal side thereof. The twist angle and &Dgr;nd of the liquid crystal are 230 to 260 degrees and 0.70 &mgr;m to 0.85 &mgr;m, respectively. &Dgr;nd of the first retardation plate is 150±50 &mgr;m, and &Dgr;nd of the second retardation plate is 610±60 nm. The angle formed by the transmission axis or absorption axis of the polarizer and the optical axis of the second retardation plate is 10 to 35 degrees, and the angle formed by the optical axis of the first retardation plate and the optical axis of the second retardation plate is 30 to 60 degrees. As a result, a bright image display having high contrast can be obtained.

Abstract: A method for fabricating STI for semiconductor device. The method includes the following steps. A trench is formed on the semiconductor substrate, a liner oxide is formed on the bottom and sidewall of the trench, and then a liner nitride is formed on the liner oxide. The first oxide layer is deposited in the trench by high density plasma chemical vapor deposition. The first oxide layer is spray-etched to a predetermined depth, wherein the recipe of the spray etching solution is HF/H2SO4=0.3˜0.4. A second oxide layer is deposited to fill the trench by high density plasma chemical vapor deposition to form a shallow trench isolation structure.