Abstract: A semiconductor device includes a substrate having a first surface, a second surface and at least one conductor part which are exposed at both the first and second surfaces of the substrate, a semiconductor chip provided on the first surface of the substrate and having a plurality of electrode pads, a plurality of leads, a plurality of bonding-wires electrically connecting the leads and the conductor parts to corresponding ones of the electrode pads of the semiconductor chip, and a resin package encapsulating the semiconductor chip, a part of the leads, and the substrate so that the conductor parts are exposed at the second surface of the substrate.

Abstract: A resonant tunneling diode is produced in a gallium arsenide material system formed with barrier layers of AlGaAs with a quantum well layer of low band-gap material between them. The material of the well is selected to adjust the second energy level to the edge of the conduction band in GaAs, with a preferred quantum well layer formed of InGaAs. The resonant tunneling diode structure is grown by a metal organic chemical vapor deposition process on the surface of the nominally exact (100) GaAs substrate. Layers of doped GaAs may be formed on either side of the multilayer resonant tunneling diode structure, and spacer layers of GaAs may also be provided on either side of the barrier layers to reduce the intrinsic capacitance of the structure.

Abstract: The present invention provides a semiconductor device, formed on a semiconductor wafer, comprising a tub, first and second active areas, and an interconnect. In one aspect of the present invention, the tub is formed in the substrate of the semiconductor wafer and first and second active areas are in contact with the tub. In one advantageous embodiment, the interconnect is formed in the tub and is in electrical contact with the first and second active areas. The interconnect extends from the first active area to the second active area to electrically connect the first and second active areas.

Abstract: An external inputting/outputting line connecting an external connection pad with an internal circuit is located along a peripheral edge of a semiconductor chip, between the edge and the external connection pad.

Abstract: A method for increasing integrated circuit density comprising stacking an upper wafer and a lower wafer, each of which have fabricated circuitry in specific areas on their respective face surfaces. The upper wafer is attached back-to-back with the lower wafer with a layer of adhesive applied over the back side of the lower wafer. The wafers are aligned so as to bring complimentary circuitry on each of the wafers into perpendicular alignment. The adhered wafer pair is then itself attached to an adhesive film to immobilize the wafer during dicing. The adhered wafer pair may be die into individual die pairs or wafer portions containing more than one dice pair. At least one face side of the die pair (attachment side) may have an array of minute solder balls or small pins disposed thereon for attachment and electrical communication of the die to at least one substrate such as a printed circuit board or leadframe.

Abstract: A method of making circuit edit structures through the backside of a flip-chip packaged integrated circuit die. In one embodiment, a circuit edit is achieved by exposing first and second circuit edit connection targets through a semiconductor substrate of the integrated circuit die from the backside. Next, a polyimide layer is vapor deposited over the first and second circuit edit connection targets and the exposed semiconductor substrate. Next, the circuit edit connection targets are re-exposed through the polyimide layer and a conductor is deposited over the re-exposed circuit edit connection targets and the deposited polyimide layer from the backside of the integrated circuit to couple together the circuit edit connection targets. The polyimide layer may act as both an insulation layer and an anti-reflective coating layer.

Abstract: An infrared detector array includes a plurality of detector pixel structures, each of which comprises a plurality of elongate quantum well infrared radiation absorbing photoconductor (QWIP) elements. The group of QWIP elements are spaced such that they comprise a diffraction grating for the received infrared radiation. Top and bottom longitudinal contacts are provided on opposite surfaces of the QWIP elongate elements to provide current flow transverse to the axis of the element to provide the required bias voltage. An optical cavity enhancement coating applied to the surface of the elements. The coating can be applied as to fill the space between the elements and extends above the top of the array if desired. The coating may be applied in multiple layers. An infrared radiation reflector is provided to form an optical cavity for receiving infrared radiation. A plurality of detector pixel structures are combined to form a focal plane array.

Abstract: A p-n junction is connected between two terminals. The p-n junction is formed between two semiconductor regions of a semiconductor with a breakdown field strength of at least 10.sup.6 V/cm. A channel region, which adjoins the p-n junction is connected in series with a silicon component between the two terminals. The channel region is provided in a first of the two semiconductor regions. A depletion zone of the p-n junction carries the reverse voltage in the off state of the silicon component.

Abstract: Light-emitting device with excellent emission intensity is difficult to obtain when gallium indium nitride with high indium composition ratio and poor crystallinity is employed as active layer for group-III nitride light-emitting device to emit a comparatively long wavelength light. The invention provides a light-emitting layer on a super lattice structure as a base layer, and crystallinity of the light-emitting layer is then improved. Furthermore, abruptness of a crystal composition at an interface of the light-emitting layer and an upper junction layer is achieved, thus forming a bending portion of a band structure expedient for allowing the emitting-layer to emit a light with a long wavelength.

Abstract: A substrate for a semiconductor package, a fabrication method for the substrate, thereof and a stacked-type semiconductor package using the substrate, and a method of making the package are disclosed. The substrate includes: an insulator having top and bottom surfaces, there being upper and lower recesses respectively formed in the top and bottom surfaces of the insulator; plural first upper and lower conductive lines respectively formed at least in part on exposed surface of the upper and lower recesses; and plural second upper and lower conductive lines respectively formed at least in part on the top and bottom surfaces and connected with corresponding ones of the first upper and lower conductive lines, respectively, the second upper and lower conductive lines extending outwardly from the upper and lower recesses, respectively.

Abstract: A specific IC layout structure for the MOSFET having a narrow and short channel, especially when the width and the length of the channel are both as small as 1 micron or less, is disclosed. In the IC layout structure, a mask includes a first mask region for defining a first active region, a second mask region for defining a second active region, and a third mask region for defining a channel region, and the third mask region is connected to the first and the second mask regions, respectively. An angle at an joint between the first mask region and the third mask region and/or an angle at an joint between the second mask region and the third mask region are/is greater than 90 degrees so that there is more space beside the channel region provided for the growth of the field oxide. Thus a 3-D oxidation thinning effect can be prevented and the properties of the MOSFET having a narrow and short channel can be stabilized.

Abstract: An MOS transistor with high output voltage endurance comprises a semiconductor substrate with the surface thereof including a doping area having a surface doping concentration decreasing from the drain connection area to the drain-side edge of the gate oxide layer. This doping area is formed by ion implantation and subsequent outdiffusion of individual partial areas. The first partial area has a size in the drain-gate extension which is considerably larger than the penetration depth of the outdiffusion in the substrate. The second partial area has a size and a distance to the first partial area which are both smaller than the penetration depth of the outdiffusion in the substrate. In the outdiffused condition, the individual diffusions originating from the individual, respectively adjacent first and second partial areas merge into each other on the surface of the substrate to thus obtain a doping concentration gradient for a constant conduction type of the doping area.

Abstract: An LDD structure of a thin film transistor for pixel switching is realized on a large glass substrate by low-temperature processes. A thin film semiconductor device for display comprises a display part and a peripheral driving part formed on a glass substrate (0). Pixel electrodes (9) and NchLDD-TFTs are arranged in a matrix in the display part. Thin film transistor PchTFTs and NchTFTs which constitute circuit elements are formed in the peripheral driving part. Each thin film transistor consists of a gate electrode (1), an insulating film (2) formed on the gate electrode (1), a polycrystalline semiconductor layer (3) formed on the insulating layer (2), and a high concentration impurity layer constituting a source (4) and a drain (7) formed on the polycrystalline semiconductor layer (3).

Abstract: The invention includes a method for assembling an integrated circuit package. In the method, a substrate is presented. Next, an integrated circuit may be mounted to the substrate. A retaining structure is presented that is shaped as a mesh that is at least one of a hexagonal mesh, a triangular mesh, and an irregular shaped mesh. The retaining structure is then impregnated with a thermal grease to form a heat pipe. The heat pipe is trimmed to the perimeter of the top surface so that the heat pipe does not extend into the at least one corner of the top surface. The heat pipe is placed on the top surface of the integrated circuit. A thermal element is then placed on the impregnated retaining structure.

Abstract: A package for mounting an integrated circuit chip to a circuit board or the like is provided. The package includes a chip carrier which has a metal substrate including first and second opposed faces. A dielectric coating is provided on at least one of the faces, which preferably is less than about 20 microns in thickness, and preferably has a dielectric constant from about 3.5 to about 4.0. Electrical circuitry is disposed on the dielectric coating, said circuitry including chip mounting pads, connection pads and circuit traces connecting the chip mounting pads to the connection pads. An IC chip is mounted by flip chip or wire bonding or adhesive connection on the face of the metal substrate which has the dielectric coating thereon. In any case, the IC chip is electrically connected to the chip mounting pads either by the solder ball or wire bond connections.

Abstract: Deposition of metal in a preferred shape, including coatings on parts, or stand-alone materials, and subsequent heat treatment to provide improved mechanical properties. In particular, the method gives products with relatively high yield strength. The products often have relatively high elastic modulus, and are thermally stable, maintaining the high yield strength at temperatures considerably above 25.degree. C. This technique involves depositing a material in the presence of a selected additive, and then subjecting the deposited material to a moderate heat treatment. This moderate heat treatment differs from other commonly employed "stress relief" heat treatments in using lower temperatures and/or shorter times, preferably just enough to reorganize the material to the new, desired form. Coating a shape and heat treating provides a shaped deposit with improved material properties.

Abstract: A multi-layer plated lead frame is provided. The lead frame has a structure in which a first precious metal plating layer, an intermediate plating layer, and a second precious metal plating layer are sequentially formed on a substrate made of ferroalloy. The lead frame shows improvement in all properties including wire bonding, anti-corrosion, and solderability.

Abstract: A voltage-driven power semiconductor device includes a voltage-driven IEGT chip, a collector electrode plate, an emitter electrode plate, and an inductance material. The collector electrode plate is connected to the collector of the IEGT chip, and press-contacts the IEGT chip from its collector side. The emitter electrode plate press-contacts the IEGT chip from its emitter side. The inductance material has an inductance component and connects the emitter of the IEGT chip and the emitter electrode plate. In the voltage-driven power semiconductor device having this arrangement, an induced electromotive force is generated in the inductance material arranged between the emitter of the IEGT chip and the emitter electrode plate. This induced electromotive force can suppress a steep current change (di/dt) upon an OFF operation, and can further suppress a steep voltage change (dv/dt) caused by the current change (di/dt).

Abstract: An SRAM is provided with a high-resistance element for loading including a high-resistance portion, which extends onto adjacent memory cell. An interlayer insulating film is formed between the high-resistance portions.

Abstract: A gallium nitride (GaN)-based semiconductor device comprises a substrate, a single-crystal layer consisting mainly of GaN with a magnesium (Mg) concentration of N.sub.bg1 cm.sup.-3, the single-crystal layer being provided near the substrate and having a thickness of d.sub.1 .mu.m, and a semiconductor layer consisting mainly of Ga.sub.1-x Al.sub.x N having an Al composition x of at least 0.02 and not higher than 1 and having a thickness of d.sub.2 .mu.m. The single-crystal layer is situated between the substrate and the semiconductor layer, and Mg is added to the semiconductor layer at a concentration of N.sub.Mg cm.sup.-3. The Al composition x, the concentration N.sub.Mg, the concentration N.sub.bg1, the thickness d.sub.1 and the thickness d.sub.2 have the following relationshipd.sub.1 /(1600.times.x)<d.sub.2 <3.6.times.10.sup.-3 .times.logN/(x+0.02)+0.02wherein when N.sub.Mg >N.sub.bg1, N cm.sup.-3 =N.sub.Mg -N.sub.bg1, and when N.sub.Mg .ltoreq.N.sub.