Abstract: A semiconductor wafer testing fixture facilitates burn-in testing of multiple wafers, whereby individual wafers have an array of individual die or integrated circuit chips with their own test circuitry. The wafer has Vcc and Vss buses provided thereon which are coupled to the individual integrated circuit chips and test circuitry. The fixture has a housing sized to accommodate multiple semiconductor wafers in a selected orientation. The wafers are supported within the housing on corresponding shelves, which provides a back bias voltage to the wafer. The fixture has first and second conductive arms for supplying selected voltages to the Vcc and Vss buses for imparting test cycling of the integrated circuits. The first arm has multiple hands which engage the Vcc buses on the wafers supported on corresponding shelves. Likewise, the second arm has multiple second hands which engage the Vss buses on the wafers supported on corresponding shelves.

Abstract: An LED device includes at least one LED chip having a front contact metallization disposed on a light exit surface of a light-emitting member and a rear contact metallization disposed on a side of the light-emitting member opposite the light exit surface. The LED chip is disposed between first and second conductor track supports. The first conductor track support is transparent and has at least one first electric conductor contacting the front contact metallization. The second conductor track support has at least one second electric conductor contacting the rear contact metallization. The LED device has, inter alia, the special advantage of permitting the size of the LED chips to be reduced, in contrast with the chip size in conventional LED devices, thus allowing the luminous spot density to be increased.

Abstract: On a substrate of n-type GaAs, an n-type cladding layer of n-type Zn.sub.0.9 Mg.sub.0.1 S.sub.0.13 Se.sub.0.87, an n-type light guiding layer of n-type ZnS.sub.0.06 Se.sub.0.94, an active layer of ZnCdSe and a p-type light guiding layer of p-type ZnS.sub.0.06 Se.sub.0.94 are successively formed. On the p-type light guiding layer, a p-type contact structure is formed. The p-type contact structure includes a first layer of p-type ZnS.sub.0.31 Se.sub.0.54 Te.sub.0.15, a second layer of ZnS.sub.0.47 Se.sub.0.28 Te.sub.0.25, a third layer of p-type ZnS.sub.0.65 Te.sub.0.35, a fourth layer of p-type ZnS.sub.0.5 Te.sub.0.5 and a fifth layer of p-type ZnTe.

Abstract: High power semiconductor module device constituted in such a manner that a circuit board to which semiconductor pellets are bonded is bonded onto a heat sink, and an electrically insulating case with elasticity which has a tubular portion surrounding the sides of the circuit board is mounted on the heat sink, wherein there is provided a push member which is composed of an electrically insulating material and pushes the respective pellet wholly or partially from above with a predetermined pressure. By thus pushing the pellet by means of the push member, the destruction of the module device due to the thermal fatigue of the bonded portions of the circuit board and the pellets, the bonded portion of the circuit board and heat sink, and the bonded portions of the bonding wires is prevented even when the temperature of the whole module is repeatedly raised and lowered by the repetition of heating and cooling during the operation of the pellets.

Abstract: An insulating film between stacked electrically conducting layers through which interconnections of integrated circuits are realized, is formed of an aerogel of an inorganic oxide on which organic monomers have been grafted under inert ion bombardment and successively further incorporated in the aerogel to fill at least partially the porosities of the inorganic aerogel. The composite dielectric material is thermally stable and has a satisfactory thermal budget. The method of forming an aerogel film includes the spinning of a precursor compound solution onto the wafer followed by supercritical solvent extraction carried out in the spinning chamber.

Abstract: Crack stops for substantially preventing cracks and chips produced along the dicing channel from spreading into the active areas of the ICs are described. The crack stops are formed by creating discontinuities in the thickness of the dielectric layer in the dicing channel near the chip edges. The discontinuities can result in increasing and/or decreasing the thickness of the dielectric layer.

Abstract: A metallization structure comprises a semiconductor substrate and pre-formed multi-interconnect layer, which include a passivation layer deposited on the top copper layer of the multi-interconnect layer, a pad window, and a non-copper thin conductive film. The non-copper thin conductive film is deposited in the pad window to protect the top copper layer from exposure to the air. The non-copper thin conductive film includes aluminum, tantalum, TaN, TiN, or WN.

Abstract: A pressure assembled power module is provided with first and second die, the first and second die being stacked atop one another and sandwiched between first and second conductive sheets, where the die are separated by a relatively flat central conductive lead. Integral to the central conductive lead are spring elements which bias the die against both the conductive sheets and the central conductive lead. Consequently, electrical and thermal interconnections are achieved between semiconductor devices and between the semiconductor devices and a heat sink or substrate.

Abstract: A thermal conducting material for providing lateral thermal conduction across a surface of an integrated circuit and for enhancing thermal dissipation from the integrated circuit. The integrated circuit is incorporated within a semiconductor device having a cavity package. A layer of the thermal conducting material, preferably electrically non-conductive, is disposed on a surface of an integrated circuit in the form of a die to provide lateral heat conduction to reduce the number of hot spots within the integrated circuit. Alternatively, the thermal conducting, electrically non-conductive material may be used to fill a cavity within the cavity package so that the cavity package dissipates heat in a more effective manner.

Abstract: An integrated circuit and a method of making a transistor thereof are provided. The integrated circuit includes a substrate and a plurality of transistors positioned on a plurality of active areas. Each of the transistors has a gate dielectric layer with a V-shaped cross-section positioned on one of the plurality of active areas, a gate electrode positioned on the gate dielectric layer, a first source/drain region positioned in the substrate, and a second source/drain region positioned in the substrate in spaced-apart relation to the first source/drain region to define a channel region beneath the gate dielectric layer. The V-shaped gate dielectric layer requires less horizontal substrate area, enabling higher packing density for a given substrate.

Abstract: A surface mount semiconductor package employs locking elements for locking a plastic housing to a metal pad on which a semiconductor device is mounted. The package includes terminals having elongated crushable beads on their side surfaces adjacent the portions of the terminals just outside the plastic housing. The beads are crushed inwardly by a molding tool when it closes to provide a seal which prevents the molding plastic from bleeding out and over the sides of the terminals which extend beyond the housing and which could interfere with solder connection to the terminals.

Abstract: A device includes a chip, and a resin package sealing the chip, the resin package having resin projections located on a mount-side surface of the resin package. Metallic films are respectively provided to the resin projections. Connecting parts electrically connect electrode pads of the chip and the metallic films.

Abstract: Nitrogen-containing III-V alloy semiconductor materials have both a conduction band offset .DELTA.Ec and a valence band offset .DELTA.Ev large enough for the practical applications to light emitting devices. The semiconductor materials are capable of providing laser diodes, having excellent temperature characteristics with emission wavelengths in the red spectral region and of 600 nm or smaller, and high brightness light emitting diodes with emission wavelengths in the visible spectral region. The light emitting device is fabricated on an n-GaAs substrate, which has the direction normal to the substrate surface is misoriented by 15.degree. from the direction normal to the (100) plane toward the [011] direction. On the substrate, there disposed by MOCVD, for example, are an n-GaAs buffer layer, an n-(Al.sub.0.7 Ga.sub.0.3).sub.0.51 In.sub.0.49 P cladding layer, an (Al.sub.0.2 Ga.sub.0.8).sub.0.49 In.sub.0.51 N.sub.0.01 P.sub.0.99 active layer, a p-(Al.sub.0.7 Ga.sub.0.3).sub.0.51 In.sub.0.

Abstract: A layer structure for a II-VI compound semiconductor device is formed on a GaAs substrate of III-V compound, wherein lattice mismatching is prevented by a first layer interposed between the GaAs substrate and a II-VI compound semiconductor active layer and made of III-V compound semiconductor including In element as a constituent element thereof. The thickness of the first layer is less than the critical thickness allowing coherent growth. Alternatively, the III-V compound of the first layer has a lattice constant substantially equal to the lattice constant of the GaAs substrate. The first layer may be a superlattice layer.

Abstract: An integrated circuit fabrication process is provided for forming a transistor in which the source/drain areas are formed simultaneously with the lightly doped drain areas. A gate electrode including a high-K gate dielectric and a gate conductor is formed upon a semiconductor substrate. The high-K gate dielectric is then selectively narrowed relative to the gate conductor. The source/drain areas and lightly doped drain areas are formed using a single impurity implant without the need for sidewall spacers on the gate electrode. A metal silicide layer may be formed across upper surfaces of the gate conductor and source/drain areas, also without the need for sidewall spacers on the gate electrode.

Abstract: Given too great a dU/dt load of a thyristor, this can trigger in uncontrolled fashion in the region of the cathode surface. Since the plasma only propagates poorly there and the current density consequently reaches critical values very quickly, there is the risk of destruction of the thyristor due to local overheating. The proposed thyristor has a centrally placed BOD structure and a plurality of auxiliary thyristors (1.-5. AG) annularly surrounding the BOD structure. The resistance of the cathode-side base (8) is locally increased under the emitter region (11) allocated to the innermost auxiliary thyristor (1. AG). Since the width (L) and the sheet resistivity of this annular zone (15) critically influences the dU/dt loadability of the first auxiliary thyristor (1.

Abstract: A read-only memory cell arrangement having planar MOS transistors which are arranged in parallel rows. Neighboring rows run alternately on the bottom of longitudinal trenches and run between neighboring longitudinal trenches. Bit lines run transversely and word lines run parallel to the longitudinal trenches. The memory cell arrangement can be produced with an area per memory cell of 2F.sup.2 (F-minimum structure size).

Abstract: A light emitting semiconductor device is provided which comprises a common substrate having a support surface, and a plurality of laminate structures formed at different regions on the support surface of the common substrate. Each of the laminate structures has at least one N-type layer, a light emitting layer and at least one P-type layer. The light emitting layer emits light at least perpendicularly to the support surface of the substrate. The laminate structures at the different regions are made to emit light of a different wavelength.

Abstract: A quantum wire switch and a switching method for switching charge carriers between a first output and a second output utilizing quantum interference of the charge carriers. A quantum switch includes a quantum wire extending from an input to a first output, a second quantum wire extending from the input to a second output, and a third quantum wire extending between the first and second outputs, the three quantum wires together defining a ring. A controllable-length quantum wire electron stub tuner is connected to the ring. As charge carriers propagate from the input around the ring the stub tuner is used to control the quantum interference of the charge carriers resulting in local maxima and minima at various points around the ring. Setting the stub to a first length results in a local maximum at the first output and a local minimum at the second output, and the charge carriers can propagate to the first output and not the second output.

Abstract: An organic electroluminescent device (1) has an organic emitter layer (5) disposed between, on the one side, a common electrode (6) and, on the other side, a first and second electrode (3A, 3B) which are mutually interlaced and independently driveable. When driven by means of, respectively, the first and second electrode (3A, 3B), respectively, a first and second pattern-wise light-emitting surface emerges. Using different light-emitting patterns, optionally in combination with light-absorbing patterns, a group of icons differing in color and/or shape can be displayed selectively using the same part of a display area.