Abstract: A semiconductor power device includes a high-resistance semiconductor substrate of the first conductivity type having first and second major surfaces and a recess in either one of the first and second major surfaces, and a semiconductor power element with a field relaxation structure, at least part of which is formed in a region of the semiconductor substrate where the recess is formed.

Abstract: A complementary heterojunction field effect transistor (CHFET) in which the channels for the p-FET device and the n-FET device forming the complementary FET are formed from gallium antimonide (GaSb) or indium antimonide (InSb). An n-type HFET structure is grown, for example, by molecular beam epitaxy (MBE) in order to obtain the highest electron or hole mobility. The complementary p-type HFET is formed by p-type doping of a cap layer thereby eliminating the need for two implants for channel doping. In order to reduce the complexity of the process for making the CHFET, a common gold germanium alloy contact is used for both the p and n-type channel devices, thereby eliminating the need for separate ohmic contacts, resulting in a substantial reduction in the number of mask levels and, thus, complexity in fabricating the device.

Abstract: Disclosed is an improved process and liner for trench isolation which includes either a single oxynitride layer or a dual oxynitride (or oxide)/nitride layer. Such a process and liner has an improved process window as well as being an effective O.sub.2 diffusion barrier and resistant to hot phosphoric and hydrofluoric acids.

Abstract: A method is provided for forming an isolation structure at a semiconducting surface of a body, and the isolation structure formed thereby. A masking layer is formed over selected regions of the substrate surface; the masking layer preferably comprising a nitride layer overlying a pad oxide layer. The masking layer is patterned and etched to form openings exposing selected regions of the substrate surface. Recesses are formed into the substrate in the openings. Preferably a portion of the pad oxide layer is isotropically etched under the nitride layer forming an undercut region. An etch stop layer is formed over the substrate in the recesses filling in the undercut along the sidewalls. A second masking layer, preferably of nitride is formed over the etch stop layer and anisotropically etched to form nitride sidewalls in the openings. The etch stop layer may be etched away from the horizontal surfaces.

Abstract: In a semiconductor integrated circuit, I/O buffer circuits that include ESD protection are generally provided for each I/O pad. According to the invention, unused pads, i.e. pads that are not connected to core circuitry according to an initial design, are connected to other pads that are used for connection to the core circuitry, thereby employing the unused pads to improve ESD protection of susceptible pads. This approach has the advantages of greater ESD protection without increasing silicon area and without adding any additional steps to the usual fabrication process. The inventive concept is especially useful for augmenting ESD protection of corner pads without requiring new or custom ESD protection circuits. This invention can be easily implemented into known layout tools.

Abstract: Disclosed in this invention is a new four-terminal type and multiple delta-doped transistors with multiple functions grown by low-pressure metalorganic chemical vapor deposition (LP-MOCVD). All the epilayers are grown on n.sup.+ -GaAs substrates. The real-space transfer transistors (RST), the collector is located under the substrate, reveal very strong negative differential resistance phenomena. The RST structure using an InGaAs channel manifests superior characteristics of a very high peak-to-valley current ratio up to 430,000 at room temperature, a peak current as high as 100 mA, very sharp charge injection, and a valley current as broad as 5.5V. Meanwhile, high performance heterostructure field effect transistors can be implemented on the same wafer by further evaporating a gate between source and drain electrodes. In order to significantly reduce leakage current, an ohmic recession is made at the source and drain.

Abstract: An electron emitting element including a semiconductor opto-electronic layer having a split valence band and capable of emitting a beam of spin-polarized electrons from an emitting surface thereof upon incidence of an excitation laser radiation upon the emitting surface, and a reflecting mirror formed on one of opposite sides of the opto-electronic layer remote from the emitting surface and cooperating with the emitting surface to effect multiple reflection therebetween of the incident laser radiation. The emitting element may be provided with a semiconductor light modulator element for modulating the intensity of the laser radiation incident upon the opto-electronic layer. A laser source may be formed integrally with the emitting element and disposed on the side of the opto-electronic layer remote from the emitting surface.

Abstract: A semiconductor process in which at least one isolation structure is formed in a semiconductor substrate is provided. An oxygen bearing species is introduced into portions of the semiconductor substrate proximal to the isolation structure, preferably through the use of an ion implantation into a tilted or inclined substrate. A gate dielectric layer is then formed on an upper surface of the semiconductor substrate. The presence of the oxygen bearing species in the proximal portions of the semiconductor substrate increases the oxidation rate of the proximal portions relative to the oxidation rate of portions of the substrate that are distal to the isolation structures. In this manner, a first thickness of the gate dielectric over the proximal portions of the semiconductor substrate is greater than a second thickness of the gate oxide layer over remaining portions of the semiconductor substrate.

Abstract: The semiconductor device comprises a low-conductivity or insulating layer (5) on one surface of which is formed a conducting section (6) while the other face is provided with a hole- or electron-type semiconductor layer (1) with an ohmic contact. A semiconductor or metal layer (2) is provided on the surface of the semiconductor layer and with (1) forms a p-n junction or Schottky barrier with another ohmic contact. The choice of the alloy cross section and thickness of the layer (1) is restricted by the condition that said layer or part of it must be fully depleted by the basic charge carriers until breakdown of the p-n junction and/or the Schottky barrier when the latter is subjected to an external bias determined by the inequality shown in the application. The p-n junction and/or Schottky barrier can be formed with a non-homogeneous dopant section along a selected X direction on the surface of the layer (1).

Abstract: A semiconductor component having a high-voltage endurance edge structure in which a multiplicity of parallel-connected individual components are disposed in a multiplicity of cells of a cell array. In an edge region, the semiconductor component has cells with shaded source zone regions. During commutation of the power semiconductor component, the shaded source zone regions suppress the switching on of a parasitic bipolar transistor caused by the disproportionately large reverse flow current density. Moreover, an edge structure having shaded source zone regions can be produced very easily in technological terms, in particular in the case of self-adjusting processes, and can thus be produced cost-effectively.

Abstract: A field effect transistor comprises: a first conductive type active layer formed on a surface region of a semiconductor substrate; first conductive type, source and drain regions formed on the semiconductor substrate on both sides of the gate electrode, the source and drain regions having a higher density of impurity than that of the active layer; and first conductive type, first and second impurity regions formed on the semiconductor substrate between a channel region below the gate electrode and the source region and between the channel region and the drain region, the first and second impurity regions having a depth, which is substantially the same as or deeper than that of those of the source region and the drain region, the first and second impurity regions having a density of impurity, which is higher than that of the channel region and lower than those of source region and the drain region.

Abstract: A composite thermal interface pad is comprised of a template portion formed from a material such as thermal gap pad material or thermal tape, in which cavities have been formed and filled with a pliable non-resilient material, such as thermal grease or thermal putty. The spacing and size of the cavities may be tailored to achieve desired elastic properties and stress distributions, as well as optimize the thermal characteristics of the thermal interface with respect to heat distribution patterns of electronic components being cooled. The composite thermal interface pad may also be used to provide EMI shielding along the gap formed between the electronic component and the adjacent cooling structure by filling closely adjacent cavities with electrically conductive non-resilient material.

Abstract: A semiconductor neuron has input electrodes are coupled capacitively to a floating gate (FG) whose potential controls the current of a MOS field effect transistor (NT). A respective neuron input (E1 . . . E4) can be connected to partial electrodes (1 . . . 7) of a respective input electrode in such a way that the total surface area of the partial electrodes connected to the respective neuron input corresponds to a respective weight of the neuron input. This results in high processing speed of a hardware neuron with the flexibility of a software neuron.

Abstract: A method is provided for a planar surface of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A conductive layer is formed over a substrate. A silicon nitride layer is formed over the conductive layer. A photoresist layer is then formed and patterned over the silicon nitride layer. The silicon nitride layer and the conductive layer are etched to form an opening exposing a portion of the substrate. The photoresist layer is then removed. The exposed substrate and a portion of the conductive layer exposed along the sidewalls in the opening are oxidized. An planarizing insulating layer such as spin-on-glass is formed over the silicon nitride layer and in the opening. The insulating layer is etched back to expose the silicon nitride wherein an upper surface of the insulating layer is level with an upper surface of the conductive layer. The silicon nitride layer is then removed. A planar silicide layer is then formed over the conductive layer.

Abstract: Disclosed is a process of electrically coupling the gate electrodes of an N-type transistor and a P-type transistor without causing substantial cross diffusion of P-type dopants into the N-type gate electrode and N-type dopants into the P-type gate electrode. This is possible because some or all annealing and diffusion steps are performed while the N-type and P-type gate electrodes are physically isolated from one another. Also disclosed is a Silicide as Diffusion Source process in which dopant atoms implanted in silicide regions diffuses out of the silicide regions and into the substrate to form source and drain diffusions. During this diffusion step adjacent N-type and P-type gate electrodes remain unconnected to prevent cross diffusion. Then, these two electrodes are electrically connected by a local interconnect. The local interconnection is a conductive path formed at about the level of the polysilicon (i.e.

Abstract: A semiconductor configuration includes a first semiconductor region which has a predetermined conductivity type and a first surface. There is a contact region disposed on the first surface of the first semiconductor region. There is a second semiconductor region disposed within the first semiconductor region underneath the contact region which has a conductivity type opposite the predetermined conductivity type of the first semiconductor region. A first p-n junction having a first depletion zone is formed between the first semiconductor region and the second semiconductor region. The second semiconductor region extends further than the contact region in all directions parallel to the first surface of the first semiconductor region to form at least one lateral channel region with a bottom in the first semiconductor region. The at least one lateral channel region is bounded toward its bottom by the first depletion zone of the first p-n junction.

Abstract: A semiconductor component of the heterojunction bipolar transistor type comprises, on a substrate, a collector, a base and a mesa-shaped emitter resting on the base. The bipolar transistor furthermore comprises electrically insulating elements in contact with the base and the flanks of the emitter mesa, said elements having a width of the same magnitude as the width of the mesa and providing the component with greater stability. Furthermore, a method for the manufacture of a component of this kind comprises in particular a step for the ion implantation of insulating ions through the constituent layer of the emitter mesa so as to define the electrically insulating elements.

Abstract: There is provided a plastic-packaged semiconductor integrated circuit including (a) an inner lead having a lead-on-chip (LOC) type structure, (b) a ball grid array (BGA) type terminals for electrically connecting the inner lead to an external circuit, and (c) an outer package made of thermosetting resin for shielding the inner lead therein.

Abstract: An aluminum pattern is formed at the same time as a gate electrode, and anodic oxide films are formed on the surfaces of the aluminum pattern and the gate electrode. After an interlayer insulating film is formed, a contact hole is formed through it. Even if the contact hole is deviated from the intended position, there occurs no failure because of the existence of the aluminum pattern on which the anodic oxide film is formed.

Abstract: A solid relay having a light emitter and a photodetector and a method of producing the same are disclosed. A planer thyristor, photodiode, phototransistor or similar photodetector is formed on an Si substrate or wafer. The surface of the photodetector is covered with an SiO.sub.2, PSG (Phospher-Silicate Glass) or similar transparent insulation film. An ITO (Indium Tin Oxide) or similar transparent film, an organic thin film and a metal electrode are sequentially formed on the transparent insulation film, constituting a light emitter. The laminate is separated from the wafer in the form of a chip by dicing. The chip is bonded to a lead frame, connected to the leads of a lead frame by wire bonding, and then sealed with epoxy resin or similar resin.