Abstract: A flexible organic light-emitting display device includes a display panel which displays an image with light, including: an organic light-emitting device which emits the light; and a plurality of organic layers stacked around the organic light-emitting device, a portion of the plurality of organic layers being exposed outside the display panel, and a metal oxide layer on the display panel, the metal oxide layer contacting the portions of the plurality of organic layers exposed outside the display panel.

Abstract: A power amplifier that includes a substrate, and an emitter layer, a base layer, and a collector layer laminated in this order on a major surface of the substrate includes an electrical insulator provided adjacent to the emitter layer, an emitter electrode provided between the substrate and both the emitter layer and the electrical insulator, a base electrode electrically connected to the base layer, and a collector electrode electrically connected to the collector layer. The emitter electrode, the electrical insulator, and the base layer are provided between the substrate and the base electrode in a direction perpendicular to the major surface of the substrate.

Abstract: A first light receiving element according to an embodiment of the present disclosure includes a plurality of pixels, a photoelectric converter that is provided as a layer common to the plurality of pixels, and contains a compound semiconductor material, and a first electrode layer that is provided between the plurality of pixels on light incident surface side of the photoelectric converter, and has a light-shielding property.

Abstract: A display device includes a pixel portion in which a pixel is arranged in a matrix, the pixel including an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen and having a channel protective layer over a semiconductor layer to be a channel formation region overlapping a gate electrode layer and a pixel electrode layer electrically connected to the inverted staggered thin film transistor. In the periphery of the pixel portion in this display device, a pad portion including a conductive layer made of the same material as the pixel electrode layer is provided. In addition, the conductive layer is electrically connected to a common electrode layer formed on a counter substrate.

Abstract: Present disclosure provides a transistor structure, including a substrate, a first gate extending along a longitudinal direction over the substrate, the first gate including a gate electrode, a second gate over the substrate and apart from the first gate, a source region of a first conductivity type in the substrate, aligning to an edge in proximity to a side of the first gate, a P-type well surrounding the source region, a drain region of the first conductivity type in the substrate, an N-type well surrounding the drain region, the second gate is entirely within a vertical projection area of the N-type well and a bottom surface of the P-type well and a bottom surface of the N-type well are substantially at a same depth from the first gate.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a first semiconductor substrate having a photodetector and a floating diffusion node. A transfer gate is disposed over the first semiconductor substrate, where the transfer gate is at least partially disposed between opposite sides of the photodetector. A second semiconductor substrate is vertically spaced from the first semiconductor substrate, where the second semiconductor substrate comprises a first surface and a second surface opposite the first surface. A readout transistor is disposed on the second semiconductor substrate, where the second surface is disposed between the transfer gate and a gate of the readout transistor. A first conductive contact is electrically coupled to the transfer gate and extending vertically from the transfer gate through both the first surface and the second surface.

Abstract: A semiconductor structure includes a semiconductor substrate and an isolation structure disposed in the semiconductor substrate. The isolation structure includes a lining layer disposed along a boundary between the semiconductor substrate and the isolation structure, a first oxide fill layer disposed over the lining layer, a dielectric barrier structure surrounding the first oxide fill layer in a closed loop, and a second oxide fill layer disposed over the dielectric barrier structure and adjacent to the lining layer.

Abstract: A semiconductor device includes a first lower line and a second lower line on a substrate, the first and second lower lines extending in a first direction, being adjacent to each other, and being spaced apart along a second direction, orthogonal the first direction, an airgap between the first and second lower lines and spaced therefrom along the second direction, a first insulating spacer on a side wall of the first lower line facing the second lower line, wherein a distance from the first airgap to the first lower line along the second direction is equal to or greater than an overlay specification of a design rule of the semiconductor device, and a second insulating spacer between the airgap and the second lower line.

Abstract: Methods, systems, and devices for vertical transistor fuse latches are described. An apparatus may include a substrate and a memory array that is coupled with the substrate. The apparatus may also include a latch that is configured to store information from a fuse for the memory array. The latch may be at least partially within an additional substrate separate from and above the substrate. The latch may include a quantity of p-type vertical transistors and a quantity of n-type vertical transistors each at least partially disposed within the additional substrate above the substrate.

Abstract: Systems, methods, and apparatuses for widened conductive line structures and staircase structures for semiconductor devices are described herein. One memory device includes an array of vertically stacked memory cells, the array including a vertical stack of horizontally oriented conductive lines. Each conductive line comprises a first portion extending in a first horizontal direction and a second portion extending in a second horizontal direction, wherein the second portion of each conductive line is of a width greater than the first portion of each conductive line.

Abstract: A display device may include a display substrate, an encapsulation substrate, and a sealing member. The display substrate may include a pixel defining layer. The sealing member may include a first portion having an inner portion between the display substrate and the encapsulation substrate and overlapping an edge portion of the pixel defining layer and an outer portion extending from the inner portion and located outside the inner portion; and a second portion between the outer portion and the display substrate.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor, and a method for forming the image sensor, in which an inter-pixel trench isolation structure is defined by a low-transmission layer. In some embodiments, the image sensor comprises an array of pixels and the inter-pixel trench isolation structure. The array of pixels is on a substrate, and the pixels of the array comprise individual photodetectors in the substrate. The inter-pixel trench isolation structure is in the substrate. Further, the inter-pixel trench isolation structure extends along boundaries of the pixels, and individually surrounds the photodetectors, to separate the photodetectors from each other. The inter-pixel trench isolation structure is defined by a low-transmission layer with low transmission for incident radiation, such that the inter-pixel trench isolation structure has low transmission for incident radiation.

Abstract: The present invention is intended to provide a semiconductor module and a semiconductor device that are compatible with various rated currents. A semiconductor module includes a lead frame, and a semiconductor element joined with the lead frame. The lead frame includes a first joining structure and a second joining structure. The first joining structure includes a void part as a part at which the lead frame does not exist, and the second joining structure includes a void part as a part at which the lead frame does not exist. Each of the first joining structure and the second joining structure has a shape such that one of the first joining structure and the second joining structure complements at least part of the void part of the other assuming that the first joining structure and the second joining structure are overlapped.

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having a bottom electrode contact for an array of vertically stacked memory cells. The bottom electrode contact is formed in a periphery region. The bottom electrode contact is electrically coupled to a number of bottom electrodes of capacitors that are also formed in the periphery region.

Abstract: A double-sided emissive transparent organic light-emitting diode display and method of manufacturing the same are provided. A double-sided emissive transparent organic light-emitting diode display includes: a substrate, a plurality of pixel areas, each including, on the substrate: a light transmitting area, and a light-emitting area, the light-emitting area including: a bottom light-emitting area including a bottom-emissive organic light-emitting diode, and a top light-emitting area including: a top-emissive organic light-emitting diode, a plurality of bottom driving elements under the top-emissive organic light-emitting diode, the bottom driving elements being configured to drive the bottom-emissive organic light-emitting diode, and a plurality of top driving elements under the top-emissive organic light-emitting diode, the top driving elements being configured to drive the top-emissive organic light-emitting diode.

Abstract: A memory cell includes: a substrate; an active layer spaced apart from a surface of the substrate and extending in a direction which is parallel to the surface of the substrate; a bit line coupled to one side of the active layer and extending in a direction perpendicular to the surface of the substrate; a capacitor coupled to another side of the active layer and spaced apart from the surface of the substrate; and a word line vertically spaced apart from the active layer and extending in a direction intersecting with the active layer, wherein the word line includes a first notch-shaped sidewall and a second notch-shaped sidewall that face each other.

Abstract: Embodiments disclosed herein include transistors and methods of forming such transistors. In an embodiment, the transistor may comprise a semiconductor channel with a first surface and a second surface opposite the first surface. In an embodiment, a source electrode may contact the first surface of the semiconductor channel and a drain electrode may contact the first surface of the semiconductor channel. In an embodiment, a gate dielectric may be over the second surface of the semiconductor channel and a gate electrode may be separated from the semiconductor channel by the gate dielectric. In an embodiment, an isolation trench may be adjacent to the semiconductor channel. In an embodiment, the isolation trench comprises a spacer lining the surface of the isolation trench, and an isolation fill material.

Abstract: A semiconductor device includes a pair of line patterns disposed on a substrate. A contact plug is disposed between the pair of line patterns and an air gap is disposed between the contact plug and the line patterns. A landing pad extends from a top end of the contact plug to cover a first part of the air gap and an insulating layer is disposed on a second part of the air gap, which is not covered by the landing pad.

Abstract: A theoretically perfectly absorbing photoconductive all-dielectric metasurface is provided. This metasurface can improve the efficiency and performance of ultrafast photoconductive switches and detectors. In an embodiment, the metasurface is incorporated in photoconductive THz switches or detectors. In embodiments, the metasurface is constituted by a network of gallium arsenide resonators. Each resonator supports two degenerate and critically coupled magnetic dipole modes. Simultaneous excitation of these two modes leads to theoretically close-to-perfect optical absorption near the resonant wavelength.

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first gate-all-around (GAA) transistor that includes a first plurality of channel members, and a second GAA transistor that includes a second plurality of channel members. The first plurality of channel members has a first pitch (P1) and the second plurality of channel members has a second pitch (P2) smaller than the first pitch (P1).