Patents Examined by John Lin
  • Patent number: 11877469
    Abstract: A display device may include a display substrate, an encapsulation substrate, and a sealing member. The display substrate may include a pixel defining layer. The sealing member may include a first portion having an inner portion between the display substrate and the encapsulation substrate and overlapping an edge portion of the pixel defining layer and an outer portion extending from the inner portion and located outside the inner portion; and a second portion between the outer portion and the display substrate.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: January 16, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seung Kim, Junehyoung Park, Jeongwoo Park, Wonsang Park
  • Patent number: 11862654
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor, and a method for forming the image sensor, in which an inter-pixel trench isolation structure is defined by a low-transmission layer. In some embodiments, the image sensor comprises an array of pixels and the inter-pixel trench isolation structure. The array of pixels is on a substrate, and the pixels of the array comprise individual photodetectors in the substrate. The inter-pixel trench isolation structure is in the substrate. Further, the inter-pixel trench isolation structure extends along boundaries of the pixels, and individually surrounds the photodetectors, to separate the photodetectors from each other. The inter-pixel trench isolation structure is defined by a low-transmission layer with low transmission for incident radiation, such that the inter-pixel trench isolation structure has low transmission for incident radiation.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Keng-Yu Chou, Wei-Chieh Chiang, Chin-Chia Kuo, Wen-Hau Wu, Hua-Mao Chen, Chih-Kung Chang
  • Patent number: 11854950
    Abstract: The present invention is intended to provide a semiconductor module and a semiconductor device that are compatible with various rated currents. A semiconductor module includes a lead frame, and a semiconductor element joined with the lead frame. The lead frame includes a first joining structure and a second joining structure. The first joining structure includes a void part as a part at which the lead frame does not exist, and the second joining structure includes a void part as a part at which the lead frame does not exist. Each of the first joining structure and the second joining structure has a shape such that one of the first joining structure and the second joining structure complements at least part of the void part of the other assuming that the first joining structure and the second joining structure are overlapped.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: December 26, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hideo Komo, Arata Iizuka, Takeshi Omaru
  • Patent number: 11849573
    Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having a bottom electrode contact for an array of vertically stacked memory cells. The bottom electrode contact is formed in a periphery region. The bottom electrode contact is electrically coupled to a number of bottom electrodes of capacitors that are also formed in the periphery region.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: December 19, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Yuichi Yokoyama, Si-Woo Lee
  • Patent number: 11832434
    Abstract: A memory cell includes: a substrate; an active layer spaced apart from a surface of the substrate and extending in a direction which is parallel to the surface of the substrate; a bit line coupled to one side of the active layer and extending in a direction perpendicular to the surface of the substrate; a capacitor coupled to another side of the active layer and spaced apart from the surface of the substrate; and a word line vertically spaced apart from the active layer and extending in a direction intersecting with the active layer, wherein the word line includes a first notch-shaped sidewall and a second notch-shaped sidewall that face each other.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: November 28, 2023
    Assignee: SK hynix Inc.
    Inventors: Seung Hwan Kim, Dong Sun Sheen, Su Ock Chung, Il Sup Jin, Seon Yong Cha
  • Patent number: 11832482
    Abstract: A double-sided emissive transparent organic light-emitting diode display and method of manufacturing the same are provided. A double-sided emissive transparent organic light-emitting diode display includes: a substrate, a plurality of pixel areas, each including, on the substrate: a light transmitting area, and a light-emitting area, the light-emitting area including: a bottom light-emitting area including a bottom-emissive organic light-emitting diode, and a top light-emitting area including: a top-emissive organic light-emitting diode, a plurality of bottom driving elements under the top-emissive organic light-emitting diode, the bottom driving elements being configured to drive the bottom-emissive organic light-emitting diode, and a plurality of top driving elements under the top-emissive organic light-emitting diode, the top driving elements being configured to drive the top-emissive organic light-emitting diode.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: November 28, 2023
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Taehan Kim, Binn Kim
  • Patent number: 11784088
    Abstract: Embodiments disclosed herein include transistors and methods of forming such transistors. In an embodiment, the transistor may comprise a semiconductor channel with a first surface and a second surface opposite the first surface. In an embodiment, a source electrode may contact the first surface of the semiconductor channel and a drain electrode may contact the first surface of the semiconductor channel. In an embodiment, a gate dielectric may be over the second surface of the semiconductor channel and a gate electrode may be separated from the semiconductor channel by the gate dielectric. In an embodiment, an isolation trench may be adjacent to the semiconductor channel. In an embodiment, the isolation trench comprises a spacer lining the surface of the isolation trench, and an isolation fill material.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: October 10, 2023
    Assignee: Intel Corporation
    Inventors: Chieh-Jen Ku, Bernhard Sell, Pei-Hua Wang, Harish Ganapathy, Leonard C. Pipes
  • Patent number: 11764107
    Abstract: A semiconductor device includes a pair of line patterns disposed on a substrate. A contact plug is disposed between the pair of line patterns and an air gap is disposed between the contact plug and the line patterns. A landing pad extends from a top end of the contact plug to cover a first part of the air gap and an insulating layer is disposed on a second part of the air gap, which is not covered by the landing pad.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: September 19, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Byoungdeog Choi, JungWoo Seo, Sangyeon Han, Hyun-Woo Chung, Hongrae Kim, Yoosang Hwang
  • Patent number: 11749694
    Abstract: A theoretically perfectly absorbing photoconductive all-dielectric metasurface is provided. This metasurface can improve the efficiency and performance of ultrafast photoconductive switches and detectors. In an embodiment, the metasurface is incorporated in photoconductive THz switches or detectors. In embodiments, the metasurface is constituted by a network of gallium arsenide resonators. Each resonator supports two degenerate and critically coupled magnetic dipole modes. Simultaneous excitation of these two modes leads to theoretically close-to-perfect optical absorption near the resonant wavelength.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: September 5, 2023
    Assignees: National Technology & Engineering Solutions of Sandia, LLC, UCL Business Ltd
    Inventors: Igal Brener, Polina Vabishchevich, Oleg Mitrofanov
  • Patent number: 11728291
    Abstract: A semiconductor arrangement in fan out packaging has a molding compound adjacent a side of a semiconductor die. A magnetic structure is disposed above the molding compound, above the semiconductor die, and around a transmission line coupled to an integrated circuit of the semiconductor die. The magnetic structure has a top magnetic portion, a bottom magnetic portion, a first side magnetic portion, and a second side magnetic portion. The first side magnetic portion and the second side magnetic portion are coupled to the top magnetic portion and to the bottom magnetic portion. The first side magnetic portion and the second side magnetic portion have tapered sidewalls.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wen-Shiang Liao, Huan-Neng Chen
  • Patent number: 11728431
    Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first gate-all-around (GAA) transistor that includes a first plurality of channel members, and a second GAA transistor that includes a second plurality of channel members. The first plurality of channel members has a first pitch (P1) and the second plurality of channel members has a second pitch (P2) smaller than the first pitch (P1).
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 11677041
    Abstract: Radiation detecting-structures and fabrications methods thereof are presented. The methods include, for instance: providing a substrate, the substrate including at least one trench extending into the substrate from an upper surface thereof; and epitaxially forming a radiation-responsive semiconductor material layer from one or more sidewalls of the at least one trench of the substrate, the radiation-responsive semiconductor material layer responding to incident radiation by generating charge carriers therein. In one embodiment, the sidewalls of the at least one trench of the substrate include a (111) surface of the substrate, which facilitates epitaxially forming the radiation-responsive semiconductor material layer. In another embodiment, the radiation-responsive semiconductor material layer includes hexagonal boron nitride, and the epitaxially forming includes providing the hexagonal boron nitride with an a-axis aligned parallel to the sidewalls of the trench.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: June 13, 2023
    Assignee: Rensselaer Polytechnic Institute
    Inventors: Rajendra P. Dahal, Ishwara B. Bhat, Yaron Danon, James Jian-Qiang Lu
  • Patent number: 11676997
    Abstract: High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
  • Patent number: 11665904
    Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell region, a channel layer in one structure penetrating the cell stacked structure, a driving transistor formed in the peripheral region, and a plug structure coupled to the driving transistor and including a stacking structure of at least two contact plugs shorter than the channel layer, wherein each of the contact plugs is arranged at a same height as a part of the cell stacked structure.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: May 30, 2023
    Assignee: SK hynix Inc.
    Inventor: Jung Ryul Ahn
  • Patent number: 11664363
    Abstract: A method for manufacturing a light emitting device including forming a plurality of first light emitting cells and a plurality of second light emitting cells on one surface of a first substrate, providing a second substrate to face the first and second light emitting cells, selectively bonding the first light emitting cells onto the second substrate, and cutting the second substrate to a mounting unit including at least two first light emitting cells.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: May 30, 2023
    Assignee: Seoul Viosys Co., Ltd.
    Inventor: Chung Hoon Lee
  • Patent number: 11665932
    Abstract: The present disclosure provided an organic light-emitting display device comprising: a substrate where a first direction and a second direction intersecting each other are defined, the substrate on which sub-pixels arranged along the first direction and the second direction; first electrodes of organic light-emitting diodes allocated respectively to the sub-pixels; a first bank having first openings exposing the first electrodes; and a second bank having second openings exposing the first electrode on the first bank, wherein in at least one region, the second opening simultaneously exposes at least two first electrodes neighboring in the third direction.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: May 30, 2023
    Assignee: LG Display Co., Ltd.
    Inventors: Dojoong Kim, Daeil Kang, Soojin Kim, Samjong Lee, Saehoon Oh, Hyungi Hong
  • Patent number: 11646341
    Abstract: A light-receiving device of an embodiment of the present disclosure includes a photoelectric conversion layer that includes a first compound semiconductor with a first conductivity type and absorbs a wavelength of an infrared region, a first semiconductor layer formed on the photoelectric conversion layer, and an insulation layer formed to surround the photoelectric conversion layer and the first semiconductor layer, the first semiconductor layer having a second conductivity-type region at a middle region excluding a periphery facing the photoelectric conversion layer.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: May 9, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yoshifumi Zaizen, Shunsuke Maruyama
  • Patent number: 11631725
    Abstract: The present disclosure provided an organic light-emitting display device comprising: a substrate where a first direction and a second direction intersecting each other are defined, the substrate on which sub-pixels arranged along the first direction and the second direction; first electrodes of organic light-emitting diodes allocated respectively to the sub-pixels; a first bank having first openings exposing the first electrodes; and a second bank having second openings exposing the first electrode on the first bank, wherein in at least one region, the second opening simultaneously exposes at least two first electrodes neighboring in the third direction.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: April 18, 2023
    Assignee: LG Display Co., Ltd.
    Inventors: Dojoong Kim, Daeil Kang, Soojin Kim, Samjong Lee, Saehoon Oh, Hyungi Hong
  • Patent number: 11626315
    Abstract: A planarization method includes forming a dielectric layer over a polish stop layer. The dielectric layer is polished until reaching the polish stop layer, and the polished dielectric layer has a concave top surface. A compensation layer is formed over the concave top surface. The compensation layer is polished.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: April 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Jung Huang, Hsu-Shui Liu, Han-Wen Liao, Yu-Yao Huang, Hsiao-Wei Chen, Yung-Lin Hsu, Kuang-Huan Hsu
  • Patent number: 11616093
    Abstract: A first light receiving element according to an embodiment of the present disclosure includes a plurality of pixels, a photoelectric converter that is provided as a layer common to the plurality of pixels, and contains a compound semiconductor material, and a first electrode layer that is provided between the plurality of pixels on light incident surface side of the photoelectric converter, and has a light-shielding property.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: March 28, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shuji Manda, Ryosuke Matsumoto, Suguru Saito, Shigehiro Ikehara, Tetsuji Yamaguchi, Shunsuke Maruyama