Patents Examined by John Lin
  • Patent number: 10811360
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, an insulating film, a first interconnect, a conductor, and a frame-shaped portion. The insulating film is provided on the semiconductor layer. The first interconnect is provided on the insulating film. The conductor extends through the insulating film and electrically connects the semiconductor layer and the first interconnect. The frame-shaped portion extends through the insulating film and is provided in a second region different from a first region, the conductor being provided in the first region. The frame-shaped portion protrudes from a surface of the insulating film on which the first interconnect is provided.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: October 20, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Masayoshi Tagami
  • Patent number: 10784361
    Abstract: A semiconductor device according to an embodiment includes a first GaN-based semiconductor layer, a second GaN-based semiconductor layer provided on the first GaN-based semiconductor layer and having a wider band gap than the first GaN-based semiconductor layer, a source electrode electrically connected to the second GaN-based semiconductor layer, a drain electrode electrically connected to the second GaN-based semiconductor layer, a gate electrode provided between the source electrode and the drain electrode, and a passivation film provided on the second GaN-based semiconductor layer between the source electrode and the gate electrode and between the gate electrode and the drain electrode, the passivation film including a first insulating film and a second insulating film, the first insulating film including nitrogen, the first insulating film having a thickness equal to or greater than 0.2 nm and less than 2 nm, the second insulating film including oxygen and provided on the first insulating film.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: September 22, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisashi Saito, Miki Yumoto
  • Patent number: 10773953
    Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: September 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Meng-Jia Lin, Yung-Hsiao Lee, Weng-Yi Chen, Shih-Wei Li, Chung-Hsien Liu
  • Patent number: 10727197
    Abstract: An embedded-bridge substrate connector apparatus includes a patterned reference layer to which a first module and a subsequent module are aligned and the two modules are mated at the patterned reference layer. At least one module includes a silicon bridge connector that bridges to two devices, through the patterned reference layer, to the mated module.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: July 28, 2020
    Assignee: Intel IP Corporation
    Inventors: Bernd Waidhas, Georg Seidemann, Andreas Wolter, Thomas Wagner, Stephan Stoeckl, Laurent Millou
  • Patent number: 10686032
    Abstract: High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
  • Patent number: 10685854
    Abstract: A structure includes a thermal interface material, and a Perforated Foil Sheet (PFS) including through-openings therein, with a first portion of the PFS embedded in the thermal interface material. An upper layer of the thermal interface material is overlying the PFS, and a lower layer of thermal interface material is underlying the PFS. The thermal interface material fills through-openings in the PFS.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wensen Hung
  • Patent number: 10680105
    Abstract: A method of fabricating a symmetric element of a resistive processing unit (RPU) includes forming a substrate with a channel region connecting two doped regions, and forming a source above one of the two doped regions and a drain above the other of the two doped regions. A gate is formed above the channel region, and a bar ferroelectric is disposed above the channel region and below the gate.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jin-Ping Han, Ramachandran Muralidhar, Dennis M. Newns, Paul M. Solomon
  • Patent number: 10680066
    Abstract: Example embodiments relate to a graphene device, methods of manufacturing and operating the same, and an electronic apparatus including the graphene device. The graphene device is a multifunctional device. The graphene device may include a graphene layer and a functional material layer. The graphene device may have a function of at least one of a memory device, a piezoelectric device, and an optoelectronic device within the structure of a switching device/electronic device. The functional material layer may include at least one of a resistance change material, a phase change material, a ferroelectric material, a multiferroic material, multistable molecules, a piezoelectric material, a light emission material, and a photoactive material.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: June 9, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinseong Heo, Kiyoung Lee, Seongjun Park
  • Patent number: 10665609
    Abstract: The present invention is notably directed to an electro-optical device. The latter comprises a layer structure with: a silicon substrate; a buried oxide layer over the silicon substrate; a tapered silicon waveguide core over the buried oxide layer, the silicon waveguide core cladded by a first cladding structure; a bonding layer over the first cladding structure; and a stack of III-V semiconductor gain materials on the bonding layer, the stack of III-V semiconductor gain materials cladded by a second cladding structure. The layer structure is configured to optically couple radiation between the stack of III-V semiconductor gain materials and the tapered silicon waveguide core. The first cladding structure comprises a material having: a refractive index that is larger than 1.54 for said radiation; and a bandgap, which, in energy units, is larger than an average energy of said radiation.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: May 26, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Utz Herwig Hahn, Marc Seifried
  • Patent number: 10644654
    Abstract: Structures for a cascode integrated circuit and methods of forming such structures. A field-effect transistor of the structure includes a gate electrode finger, a first source/drain region, and a second source/drain region. A bipolar junction transistor of the structure includes a first terminal, a base layer with an intrinsic base portion arranged on the first terminal, and a second terminal that includes one or more fingers arranged on the intrinsic base portion of the base layer. The intrinsic base portion of the base layer is arranged in a vertical direction between the first terminal and the second terminal. The first source/drain region is coupled with the first terminal, and the first source/drain region at least partially surrounds the bipolar junction transistor.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Vibhor Jain, Anthony K. Stamper, Alvin J. Joseph, John J. Pekarik
  • Patent number: 10615255
    Abstract: A method of fabricating a semiconductor structure includes forming a plurality of semiconductor fins disposed on a semiconductor substrate, wherein at least one of the fins is an unwanted fin including a semiconductor material; providing a conformal protective layer over the plurality of semiconductor fins; forming a mask having an opening over the unwanted fin; removing a portion of the unwanted fin to expose a fin spike; oxidizing the fin spike to form an oxidized semiconductor material; and removing the oxidized semiconductor material to expose a fin base.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: April 7, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC., SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Susan S. Fan, Dongseok Lee, David Moreau, Tenko Yamashita
  • Patent number: 10564498
    Abstract: Display systems and related methods involving bus lines with low capacitance cross-over structures are provided. A representative display system includes: a first structure comprising: a plurality of scan lines extending in a first direction; and a plurality of data lines extending in a second direction and crossing over the scan lines at respective cross-over locations, each of the plurality of data lines having a pair of side walls spaced apart from each other at each of the cross-over locations, with each of the side walls exhibiting a height higher than portions of the data lines not located at the cross-over locations.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: February 18, 2020
    Assignee: A.U. VISTA INC.
    Inventor: Lee Seok Lyul
  • Patent number: 10559599
    Abstract: A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: February 11, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Rihito Wada, Yoko Chiba
  • Patent number: 10535743
    Abstract: A vertical power semiconductor component includes a semiconductor chip, the semiconductor chip having a top main surface and a bottom main surface. Each of said top main surface and said bottom main surface is in a heat exchanging relationship with a top metallization layer and a bottom metallization each of which serving as a heat sink. Each of said top metallization layer and said bottom metallization layer have a layer thickness of at least 15 ?m and have a specific heat capacity per volume that is at least a factor of 1.3 higher than the specific heat capacity per volume of the semiconductor chip. Each of said top metallization layer and said bottom metallization layer serving as a heat sink contacts the respective main surface via a respective diffusion barrier layer.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: January 14, 2020
    Assignee: Infineon Technologies AG
    Inventors: Frank Hille, Hans-Joachim Schulze
  • Patent number: 10510688
    Abstract: The present disclosure relates to an integrated circuit having a via rail that prevents reliability concerns such as electro-migration. In some embodiments, the integrated circuit has a first plurality of conductive contacts arranged over a semiconductor substrate. A first metal interconnect wire is arranged over the first plurality of conductive contacts, and a second metal interconnect wire is arranged over the first metal interconnect wire. A via rail is arranged over the first metal interconnect wire and electrically couples the first metal interconnect wire and the second metal interconnect wire. The via rail has a length that continuously extends over two or more of the plurality of conductive contacts. The length of via rail provides for an increased cross-sectional area both between the first metal interconnect wire and the second metal interconnect wire and along a length of the via rail, thereby mitigating electro-migration within the integrated circuit.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kam-Tou Sio, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Chi-Yeh Yu, Jiann-Tyng Tzeng, Ru-Gun Liu, Wen-Hao Chen
  • Patent number: 10504860
    Abstract: A semiconductor device includes a first circuit 1 and a second circuit 2 that are connected in series, a first terminal T1 that applies a first potential to a first power supply line DL1 of the first circuit 1, a second terminal T2 that applies a second potential to a second power supply line DL2 of the second circuit 2, a third terminal T3 that is connected to a signal transfer line of the first circuit 1, and a protection circuit that is connected to the third terminal T3, and discharges a current from the third terminal T3 to a fourth terminal T4 when a potential of the third terminal T3 becomes higher than a first threshold value. The first power supply line DL1 and the second power supply line DL2 are separated, and the fourth terminal T4 is not directly connected to the first power supply line DL1 and is electrically connected to a lead.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: December 10, 2019
    Assignee: THINE ELECTRONICS, INC.
    Inventors: Shunichi Kubo, Yoshinobu Oshima, Masaki Mitarai
  • Patent number: 10490566
    Abstract: A memory device includes a cell region and a peripheral circuit region adjacent the cell region. A plurality of gate electrode layers and insulating layers are stacked on the substrate in the cell region, and a plurality of circuit devices are in the peripheral circuit region. A first interlayer insulating layer is on the substrate in the peripheral circuit region and covers the plurality of circuit devices, and a second interlayer insulating layer is on the substrate in the cell region and the peripheral circuit region. A blocking layer is on the plurality of circuit devices between the first and second interlayer insulating layers. The blocking layer is on an upper surface, of the first interlayer insulating layer, and a side surface of the blocking layer is covered by the second interlayer insulating layer.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: November 26, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won Seok Jung, Brad H. Lee, Sang Woo Jin
  • Patent number: 10490444
    Abstract: A semiconductor device includes a pair of line patterns disposed on a substrate. A contact plug is disposed between the pair of line patterns and an air gap is disposed between the contact plug and the line patterns. A landing pad extends from a top end of the contact plug to cover a first part of the air gap and an insulating layer is disposed on a second part of the air gap, which is not covered by the landing pad.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: November 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoungdeog Choi, JungWoo Seo, Sangyeon Han, Hyun-Woo Chung, Hongrae Kim, Yoosang Hwang
  • Patent number: 10488716
    Abstract: A liquid crystal display device includes a gate line in a first direction, a data line in a second direction intersecting the first direction, a pixel including a first region having a transistor connected to the gate and data lines, and a contact hole connecting the transistor to a pixel electrode, and a second region having the pixel electrode, wherein a length of a first width along the first direction on the first region is longer than a length of a second width along the second direction on the first region, and wherein a length of a third width along the first direction on the second region is longer than a length of a fourth width along the second direction on the second region.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: November 26, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyung Jin Song, Kyung Ho Kim, Kee Bum Park, Dong Hee Shin
  • Patent number: 10475785
    Abstract: According to one embodiment, the insulating film is provided between the anode region and the cathode region in the surface of the second semiconductor region. The third semiconductor region is provided inside the second semiconductor region. The third semiconductor region covers a corner of the insulating film on the anode region side. The first electrode contacts the anode region and the third semiconductor region. The second electrode contacts the cathode region. The third electrode is provided on the insulating film and positioned on a p-n junction between the second semiconductor region and the third semiconductor region.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: November 12, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keita Takahashi