Patents Examined by John Lin
  • Patent number: 10431699
    Abstract: In one embodiment, a trench Schottky rectifier includes a termination trench and active trenches provided in a semiconductor layer. A first active trench is configured to be at a shallower depth than the termination trench to provide a trench depth difference. A second active trench is configured to be at a depth similar to the termination trench. The selected trench depth difference in combination with one or more of the other second active trench depth, the dopant concentration of the semiconductor layer, the thickness of the semiconductor layer, first active trench width to termination trench width, and/or dopant profile of the semiconductor layer provide a semiconductor device having improved performance characteristics.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: October 1, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mohammed Tanvir Quddus, Mihir Mudholkar, Michael Thomason
  • Patent number: 10431152
    Abstract: A top-emission organic light-emitting display device includes a plurality of pixels each having color filters. Each of the plurality of pixels comprises a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. The first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are arranged sequentially in a column direction. Each of the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel is extended in a row direction rather than in the column direction.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: October 1, 2019
    Assignee: LG Display Co., Ltd.
    Inventor: KyungMan Kim
  • Patent number: 10388538
    Abstract: An object of the present invention to provide a highly reliable semiconductor device. Another object is to provide a manufacturing method of a highly reliable semiconductor device. Still another object is to provide a semiconductor device having low power consumption. Yet another object is to provide a manufacturing method of a semiconductor device having low power consumption. Furthermore, another object is to provide a semiconductor device which can be manufactured with high mass productivity. Another object is to provide a manufacturing method of a semiconductor device which can be manufactured with high mass productivity. An impurity remaining in an oxide semiconductor layer is removed so that the oxide semiconductor layer is purified to have an extremely high purity. Specifically, after adding a halogen element into the oxide semiconductor layer, heat treatment is performed to remove an impurity from the oxide semiconductor layer. The halogen element is preferably fluorine.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: August 20, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideyuki Kishida
  • Patent number: 10381468
    Abstract: A semiconductor device includes a single electron transistor (SET) having an island region, a bottom source/drain region under the island region, and a top source/drain region over the island region, a first gap between the bottom source/drain region and the island region, a second gap between the top source/drain region and the island region, and a gate structure on a side of the island region.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10374079
    Abstract: A silicon carbide semiconductor device includes: a substrate; a drift layer over the substrate; a base region over the drift layer; multiple source regions over an upper layer portion of the base region; a contact region over the upper layer portion of the base region between opposing source regions; multiple trenches from a surface of each source region to a depth deeper than the base region; a gate electrode on a gate insulating film in each trench; a source electrode electrically connected to the source regions and the contact region; a drain electrode over a rear surface of the substrate; and multiple electric field relaxation layers in the drift layer between adjacent trenches. Each electric field relaxation layer includes: a first region at a position deeper than the trenches; and a second region from a surface of the drift layer to the first region.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: August 6, 2019
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hirotaka Saikaku, Jun Sakakibara, Shoji Mizuno, Yuichi Takeuchi
  • Patent number: 10297631
    Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) structure having a conductive blocking structure configured prevent radiation produced by a device within a first die from affecting an image sensing element within a second die. The IC structure has a first IC die with one or more semiconductor devices and a second IC die with an array of image sensing elements. A hybrid bonding interface region is arranged between the first and second IC die. A conductive bonding structure is arranged within the hybrid bonding interface region and is configured to electrically couple the first IC die to the second IC die. A conductive blocking structure is arranged within the hybrid bonding interface region and extends laterally between the one or more semiconductor devices and the array of image sensing elements.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ying Ho, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Yan-Chih Lu
  • Patent number: 10276518
    Abstract: A semiconductor arrangement in fan out packaging has a molding compound adjacent a side of a semiconductor die. A magnetic structure is disposed above the molding compound, above the semiconductor die, and around a transmission line coupled to an integrated circuit of the semiconductor die. The magnetic structure has a top magnetic portion, a bottom magnetic portion, a first side magnetic portion, and a second side magnetic portion. The first side magnetic portion and the second side magnetic portion are coupled to the top magnetic portion and to the bottom magnetic portion. The first side magnetic portion and the second side magnetic portion have tapered sidewalls.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wen-Shiang Liao, Huan-Neng Chen
  • Patent number: 10263035
    Abstract: An MRAM device includes a lower electrode on a substrate, an MTJ structure on the lower electrode, a metal oxide pattern on the MTJ structure, a conductive pattern on at least a portion of a sidewall of the metal oxide pattern, and an upper electrode on the metal oxide pattern and the conductive pattern. The conductive pattern has a thickness varying along the sidewall of the metal oxide pattern in a plan view.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: April 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Ahn, Ji-Su Ryu, Seung-Min Lee
  • Patent number: 10224215
    Abstract: An object of the present invention to provide a highly reliable semiconductor device. Another object is to provide a manufacturing method of a highly reliable semiconductor device. Still another object is to provide a semiconductor device having low power consumption. Yet another object is to provide a manufacturing method of a semiconductor device having low power consumption. Furthermore, another object is to provide a semiconductor device which can be manufactured with high mass productivity. Another object is to provide a manufacturing method of a semiconductor device which can be manufactured with high mass productivity. An impurity remaining in an oxide semiconductor layer is removed so that the oxide semiconductor layer is purified to have an extremely high purity. Specifically, after adding a halogen element into the oxide semiconductor layer, heat treatment is performed to remove an impurity from the oxide semiconductor layer. The halogen element is preferably fluorine.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: March 5, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideyuki Kishida
  • Patent number: 10211250
    Abstract: The present disclosure relates to a solid-state image sensor and an electronic device enabling prevention of entrance of incident light from adjacent pixels and suppression of color mixture, decrease in resolution, and decrease in sensitivity. In a solid-state image sensor according to one aspect of the present disclosure, each pixel includes: these different photoelectric conversion parts configured to perform photoelectric conversion of light of a first wavelength of light of a second wavelength and a third wavelength respectively. An electrode wiring provided at a boundary of adjacent pixels, horizontally connects an electrode of at least one of the photoelectric conversion parts in one of the adjacent pixels with an electrode of the corresponding one of the photoelectric conversion parts in another of the adjacent pixels and vertically connects with an electrode of at least one of the photoelectric conversion parts of each of the pixels.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: February 19, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Ryosuke Matsumoto, Masahiro Joei
  • Patent number: 10199469
    Abstract: A semiconductor device includes a silicon semiconductor layer including at least one region doped with a first conductive type dopant, a metal material layer electrically connected to the doped region, and a self-assembled monolayer (SAM) between the doped region and the metal material layer, the SAM forming a molecular dipole on an interface of the silicon semiconductor layer in a direction of reducing a Schottky barrier height (SBH).
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: February 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seunggeol Nam, Hyeonjin Shin, Yeonchoo Cho, Minhyun Lee, Changhyun Kim, Seongjun Park
  • Patent number: 10177222
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate in which a multi-depth trench is formed, the multi-depth trench including a shallow trench and a deep trench arranged below the shallow trench, a first dielectric material formed in partial area of the multi-depth trench, the first dielectric material including a slope in the shallow trench that extends upward from a corner where a bottom plane of the shallow trench and a sidewall of the deep trench meets, the slope being inclined with respect to the bottom plane of the shallow trench, and a second dielectric material formed in areas of the multi-depth trench in which the first dielectric material is absent.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: January 8, 2019
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventors: Yong-sik Won, Sang-uk Lee
  • Patent number: 10170471
    Abstract: A semiconductor device, having a heterogeneous silicon stack, wherein the heterogeneous silicon stack comprises at least a base layer, a doped silicon layer, and an undoped silicon layer. The semiconductor device further includes a plurality of silicon fins atop a doped silicon oxide fin layer and an undoped silicon oxide fin layer, wherein the plurality of silicon fins have a uniform width along the height of the plurality of silicon fins, and wherein the plurality of silicon fins have a plurality of hard mask caps.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Hong He, Sivananda K. Kanakasabapathy, Chiahsun Tseng, Yunpeng Yin
  • Patent number: 10147753
    Abstract: A stacked image sensor includes: a lower device including a lower inter-layer dielectric layer over an upper surface of a lower substrate, and a lower capping layer over the lower inter-layer dielectric layer; an upper device stacked over the lower device, including photodiodes in an upper substrate, an upper inter-layer dielectric layer below a lower surface of the upper substrate, and an upper capping layer below the upper inter-layer dielectric layer; and an air gap formed between the lower inter-layer dielectric layer and the upper inter-layer dielectric layer.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: December 4, 2018
    Assignee: SK Hynix Inc.
    Inventors: Yun-Hui Yang, Seon-Man Hwang
  • Patent number: 10032796
    Abstract: A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: July 24, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Rihito Wada, Yoko Chiba
  • Patent number: 10032950
    Abstract: An avalanche photodiode, and related method of manufacture and method of use thereof, that includes a first contact layer; a multiplication layer, wherein the multiplication layer includes AlInAsSb; a charge, wherein the charge layer includes AlInAsSb; an absorption, wherein the absorption layer includes AlInAsSb; a blocking layer; and a second contact layer.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: July 24, 2018
    Assignee: University of Virginia Patent Foundation
    Inventors: Joe C. Campbell, Min Ren, Madison Woodson, Yaojia Chen, Seth Bank, Scott Maddox
  • Patent number: 9972756
    Abstract: A method for producing a semiconductor light-emitting device having a substrate, an element and an encapsulating material as constituent members, includes: a first step of providing the substrate with the element; a second step of potting an uncured encapsulating material onto the substrate to cover the element; and a third step of curing the potted encapsulating material in such a manner that all of the following formulae (1), (2) and (3) are satisfied when the absorbances which a cured encapsulating material having a thickness of t [nm] has at wavelengths of 380 nm, 316 nm and 260 nm are represented by AbsA(t), AbsB(t) and AbsC(t), respectively, and the light transmittance thereof at 380 nm is represented by T(t): (1) T(1.7)?90%; (2) AbsB(t)?AbsA(t)<0.011t; and (3) AbsC(t)?AbsA(t)<0.125t.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: May 15, 2018
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Gaku Yoshikawa, Masayuki Takashima
  • Patent number: 9960177
    Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell region, a channel layer in one structure penetrating the cell stacked structure, a driving transistor formed in the peripheral region, and a plug structure coupled to the driving transistor and including a stacking structure of at least two contact plugs shorter than the channel layer, wherein each of the contact plugs is arranged at a same height as a part of the cell stacked structure.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: May 1, 2018
    Assignee: SK hynix Inc.
    Inventor: Jung Ryul Ahn
  • Patent number: 9947662
    Abstract: A CMOS circuit comprises CMOS MOSFETs having n-type and p-type gates on the same substrate, wherein the substrate is divided into regions of n-type and p-type diffusions, and those diffusions are contained within a deeper n-type diffusion, used to junction isolate components within the deeper n-type diffusion from components outside of the deeper n-type diffusion.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: April 17, 2018
    Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AG
    Inventors: Paul Ronald Stribley, John Nigel Ellis
  • Patent number: 9806026
    Abstract: The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: October 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Tien-I Bao