Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells. The vertically stacked memory cells have horizontally oriented access devices having a first source/drain region, a channel region, and a second source drain and horizontally oriented storage nodes that are vertically separated from the access devices. Vertically oriented gates are separated from the respective channel regions by gate dielectrics, and horizontally oriented digit lines are coupled to respective first source/drain regions. The horizontally oriented storage nodes each have a first electrode coupled to the second source/drain regions of the access devices and each first electrode opposes two different sides of the horizontal access devices including an electrical contact with a vertical side of the second source/drain regions.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin spacer alongside a fin structure, a source/drain structure over the fin structure, and a salicide layer along a surface of the source/drain structure. A bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a capping layer over the salicide layer. A portion of the capping layer directly below the bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a dielectric layer over the capping layer. The dielectric layer is made of a different material than the capping layer.

Abstract: A sensing device includes a flexible substrate, a reflective layer, a planarization layer, plural switching elements and plural sensing elements. The flexible substrate has plural recesses on a surface. The reflective layer is located on the flexible substrate and conforms to an inner surface of the plural recesses. The planarization layer is disposed on the reflective layer. The plural switching elements are disposed on the planarization layer. The plural sensing elements are disposed on the planarization layer and electrically connected to the plural switching elements respectively. A method for fabricating a sensing device is also provided.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate, multiple active pillars located in the substrate, and multiple word lines. The multiple active pillars are arranged in an array in a first direction and a second direction. The first direction and the second direction are both directions parallel to a top surface of the substrate, and the first direction and the second direction intersect. The multiple word lines are spaced apart in the first direction. Each of the word lines extends in the second direction and continuously surrounds and covers a portion of a side wall of each of the multiple active pillars arranged in the second direction. Any two adjacent word lines are at least partially staggered in a direction perpendicular to the top surface of the substrate.

Abstract: A semiconductor device may include a gate structure, first and second source/drain layers, first and second contact plugs, first and second conductive structures, and a third contact plug. The gate structure may be on a substrate. The first and second source/drain layers may be at upper portions, respectively, of the substrate on opposite sidewalls of the gate structure and adjacent thereto. The first and second contact plugs may be on the first and second source/drain layers, respectively, and each contact plugs may extend in a vertical direction. The first and second conductive structures may contact upper surfaces of the first and second contact plugs, respectively. The third contact plug may contact an upper surface of the second conductive structure. A height and a width of the second conductive structure may be greater than a height and a width of the first conductive structure.

Abstract: A semiconductor structure includes a substrate, a contact structure disposed on the substrate, and two first gate structures disposed on the substrate and at two sides of the first contact structure. The contact structure has a T-shaped cross-sectional profile having a first portion contacting the substrate and a second portion disposed on the first portion. A top surface of the second portion of the contact structure is flush with top surfaces of the two first gate structures.

Abstract: A package includes a substrate, a conductive layer on a first surface of the substrate forming a set of antennas, and a semiconductor die forming communication channels for the antennas, each of the communication channels being electrically coupled to the antennas by way of a redistribution layer that includes the substrate, the semiconductor die being mounted on either the first surface or an opposing second surface of the substrate. The package further includes a set of electrical contacts on the second surface of the substrate, the redistribution layer further coupling the set of electrical contacts to the semiconductor die. The package further includes a stiffening layer over the first surface of the substrate, the stiffening layer forming gaps over the antennas such that the antennas are on an outer surface of the package.

Abstract: Embodiments provide a transistor and a method for manufacturing same, a semiconductor device and a method for manufacturing same. The method for manufacturing a transistor includes operations. A wafer is provided, the wafer has multiple transistor formation regions, each of which has a transistor pillar with an exposed gate formation surface. A gate oxide layer and a gate are sequentially formed on the gate formation surface of each of the transistor pillars. A source is formed at a first end of each of the transistor pillars. A drain is formed at a second end of each of the transistor pillars, here the first end and the second end are opposite ends of each of the transistor pillars in a first direction which is a thickness direction of the wafer; a part of each of the transistor pillars between the source and the drain forms a channel region of the transistor.

Abstract: A semiconductor memory device and method for making the same. The semiconductor memory device includes an active layer spaced apart from a substrate, extending in a direction parallel to the substrate, and including a channel; a bit line extending in a vertical direction to the substrate and contacting a first end portion of the active layer; a capacitor contacting a second end portion of the active layer; a word line including a high work function electrode adjacent to the bit line and a low work function electrode adjacent to the capacitor; a first gate dielectric layer disposed between the low work function electrode and the active layer; and a second gate dielectric layer disposed between the high work function electrode and the active layer, the second gate dielectric layer being thinner than the first gate dielectric layer.

Abstract: A display device is disclosed, which may display an image even in an area overlapped with a camera and have high light transmittance. The display device comprises a substrate provided with a display area including a first display area and a second display area, a first transistor provided in the first display area over the substrate, a second transistor provided in the second display area over the substrate, a first subpixel supplied with a power source from the first transistor, and a second subpixel supplied with a power source from the second transistor. At least two or more second subpixels share one second transistor.

Abstract: An apparatus includes a substrate, a memory cell region provided over the substrate, a peripheral region provided over the substrate and adjacent to the memory cell region, and first, second, third, fourth and fifth word-lines each extending in parallel across the memory cell region and the peripheral region in numerical order. An offcut of the second word-line is interposed between edge portions of the first and third word-lines, and no offcut of the fourth word-line is interposed between edge portions of the third and fifth word-lines.

Abstract: A display panel includes a base substrate having a first surface and a second surface opposing each other, a pixel part located on the first surface, and including a plurality of pixels, and a remaining part on the second surface to cover at least a portion of the second surface, and including a moisture absorption material having a moisture absorption property.

Abstract: A JFET is provided with a very low gate current. In tests the excess gate current above the theoretical minimum current for a similarly sized reverse biased p-n junction was not observed. The JFET includes a lightly doped top gate and doped regions beneath the drain of the JFET.

Abstract: Some embodiments of the present application provide a memory forming method and a memory. The method includes: providing a substrate including at least word line structures and active regions, and bottom dielectric layers and bit line contact layers located on a top surface of the substrate, the bottom dielectric layer having bit line contact openings exposing the active regions in the substrate, and the bit line contact layers covering the bottom dielectric layers and filling the bit line contact openings; etching part of the bit line contact layers to form the bit line contact layers of different heights; forming conductive layers, top surfaces of the conductive layers being at the same height in a direction perpendicular to an extension direction of the word line structures; and the top surfaces of the conductive layers being at different heights in the extension direction of the word line structures; forming top dielectric layers.

Abstract: A structure includes a semiconductor substrate, a conductor-insulator-conductor capacitor. The conductor-insulator-conductor capacitor is disposed on the semiconductor substrate and includes a first conductor, a nitrogenous dielectric layer and a second conductor. The nitrogenous dielectric layer is disposed on the first conductor and the second conductor is disposed on the nitrogenous dielectric layer.

Abstract: A transistor, a 3D memory and a manufacturing method therefor, and an electronic device are provided in the present application. The 3D memory includes a plurality of layers of memory cells stacked in a direction perpendicular to a substrate, and a word line. A memory cell includes a transistor which includes a source and a drain, a gate extending in the direction perpendicular to the substrate, a semiconductor layer surrounding a sidewall of the gate. The semiconductor layer includes a source contact region and a drain contact region arranged at intervals. A channel between the source contact region and the drain contact region is a horizontal channel, and the word line extends in the direction perpendicular to the substrate and penetrates through the memory cells of different layers.

Abstract: The present disclosure provides a semiconductor memory device capable of improving reliability and performance. The semiconductor memory device comprises a substrate including a cell region and a peripheral region around the cell region, a cell region isolation film which defines the cell region, a bit line structure in the cell region, a first peripheral gate structure on the peripheral region of the substrate, the first peripheral gate structure comprising a first peripheral gate conduction film and a first peripheral capping film on the first peripheral gate conduction film, a peripheral interlayer insulating film around the first peripheral gate structure and an insertion interlayer insulating film on the peripheral interlayer insulating film and the first peripheral gate structure, and including a material different from the peripheral interlayer insulating film. An upper face of the peripheral interlayer insulating film is lower than an upper face of the first peripheral capping film.

Abstract: An organic light-emitting display device and method of manufacturing the same are provided. An organic light-emitting display device includes: a substrate, an organic light-emitting device on the substrate, an encapsulation layer on the substrate and the organic light-emitting device, the encapsulation layer covering the organic light-emitting device, the encapsulation layer including an encapsulation hole, a black matrix covering the encapsulation layer, the black matrix including a black matrix hole over the encapsulation hole, and a color filter in the encapsulation hole and the black matrix hole.

Abstract: A display apparatus includes an organic light-emitting device (OLED) substrate, a color control layer; a first optical layer to which the generated light of the organic light-emitting substrate is incident and from which wavelength range light is provided to the color control layer; and a second optical layer to which the wavelength-converted light of the color control layer is incident and from which display light is provided for displaying an image The first optical layer partially transmits and partially reflects light of a first wavelength range, and reflects light of a second wavelength range and light of a third wavelength range each different from the first wavelength range. The second optical layer reflects light of the first wavelength range, and transmits each of light of the second wavelength range and light of the third wavelength range.

Abstract: A flexible organic light-emitting display device includes a display panel which displays an image with light, including: an organic light-emitting device which emits the light; and a plurality of organic layers stacked around the organic light-emitting device, a portion of the plurality of organic layers being exposed outside the display panel, and a metal oxide layer on the display panel, the metal oxide layer contacting the portions of the plurality of organic layers exposed outside the display panel.