Patents Examined by John Lin
  • Patent number: 11257690
    Abstract: A structure includes a thermal interface material, and a Perforated Foil Sheet (PFS) including through-openings therein, with a first portion of the PFS embedded in the thermal interface material. An upper layer of the thermal interface material is overlying the PFS, and a lower layer of thermal interface material is underlying the PFS. The thermal interface material fills through-openings in the PFS.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wensen Hung
  • Patent number: 11251232
    Abstract: The device includes a substrate, a green light emitting element on the substrate, and a green color film layer disposed on a light exit side of the green light emitting element correspondingly, a travel distance of the light emitted from the green light emitting element in the green color film layer remains substantially unchanged with a change of a light exit angle of the light. Thus, the present disclosure can prevent a color purity of a green light passing through the green color film layer from changing, thereby improving the color shift performance of a green light passing through the green color film layer, and improving the optical performance of the green light, and thus further improving the display effect of the device and the display panel.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: February 15, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Fang He, Shi Shu
  • Patent number: 11177352
    Abstract: Example embodiments relate to a graphene device, methods of manufacturing and operating the same, and an electronic apparatus including the graphene device. The graphene device is a multifunctional device. The graphene device may include a graphene layer and a functional material layer. The graphene device may have a function of at least one of a memory device, a piezoelectric device, and an optoelectronic device within the structure of a switching device/electronic device. The functional material layer may include at least one of a resistance change material, a phase change material, a ferroelectric material, a multiferroic material, multistable molecules, a piezoelectric material, a light emission material, and a photoactive material.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: November 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jinseong Heo, Kiyoung Lee, Seongjun Park
  • Patent number: 11164899
    Abstract: An imaging device is used that has: a substrate; a first electrode layer disposed on the substrate, and having a first electrode; a first photoelectric conversion film disposed on the first electrode layer; a pixel electrode layer disposed on the first photoelectric conversion film, and having a pixel electrode; a second photoelectric conversion film disposed on the pixel electrode layer; and a second electrode layer disposed on the second photoelectric conversion film, and having a second electrode, wherein at least part of a period from among a first accumulation period during which a signal of the first photoelectric conversion film is accumulated, and a second accumulation period during which a signal of the second photoelectric conversion film is accumulated, does not overlap the other from among the first accumulation period and the second accumulation period.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: November 2, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takahiro Yamasaki, Atsushi Furubayashi
  • Patent number: 11152287
    Abstract: The present invention is intended to provide a semiconductor module and a semiconductor device that are compatible with various rated currents. A semiconductor module includes a lead frame, and a semiconductor element joined with the lead frame. The lead frame includes a first joining structure and a second joining structure. The first joining structure includes a void part as a part at which the lead frame does not exist, and the second joining structure includes a void part as a part at which the lead frame does not exist. Each of the first joining structure and the second joining structure has a shape such that one of the first joining structure and the second joining structure complements at least part of the void part of the other assuming that the first joining structure and the second joining structure are overlapped.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: October 19, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hideo Komo, Arata Iizuka, Takeshi Omaru
  • Patent number: 11139359
    Abstract: A display device includes a pixel portion in which a pixel is arranged in a matrix, the pixel including an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen and having a channel protective layer over a semiconductor layer to be a channel formation region overlapping a gate electrode layer and a pixel electrode layer electrically connected to the inverted staggered thin film transistor. In the periphery of the pixel portion in this display device, a pad portion including a conductive layer made of the same material as the pixel electrode layer is provided. In addition, the conductive layer is electrically connected to a common electrode layer formed on a counter substrate.
    Type: Grant
    Filed: October 18, 2016
    Date of Patent: October 5, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Rihito Wada, Yoko Chiba
  • Patent number: 11107744
    Abstract: An IGBT module includes a heat dissipation base plate. A first ceramic heat dissipation element is embedded in the heat dissipation base plate. A first wiring layer is provided on the surface of the heat dissipation base plate. The first side of an IGBT chip is mounted onto the first wiring layer. The second side of the IGBT chip is provided with a heat conductive metal plate. A first heat dissipation plate having a first through hole is provided on a side of the first wiring layer. The IGBT chip and the heat conductive metal plate are located in the first through hole. A second wiring layer is provided on a side of the first heat dissipation plate away from the IGBT chip. The second wiring layer is provided on a side of the heat conductive metal plate.
    Type: Grant
    Filed: January 22, 2017
    Date of Patent: August 31, 2021
    Assignee: RAYBEN TECHNOLOGIES (ZHUHAI) LIMITED
    Inventors: Shan Zhong, Weidong Gao, Qizhao Hu, Wai Kin Raymond Lam
  • Patent number: 11094784
    Abstract: A method of fabricating a semiconductor device is described. The method includes forming a stack of sacrificial layers on a substrate. A U-shaped trench is formed in the stack of the sacrificial layers. A first U-shaped channel layer is deposited in the U-shaped trench. A first U-shaped sacrificial layer is conformally formed covering the U-shaped channel layer. A second U-shaped channel layer is conformally deposited covering the first U-shaped sacrificial layer. A gate is formed around the first and the second U-shaped channel layers.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: August 17, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ruilong Xie, Julien Frougier, Chanro Park, Tenko Yamashita
  • Patent number: 11094820
    Abstract: A method of fabricating a symmetric element of a resistive processing unit (RPU) includes forming a substrate with a channel region connecting two doped regions, and forming a source above one of the two doped regions and a drain above the other of the two doped regions. A gate is formed above the channel region, and a bar ferroelectric is disposed above the channel region and below the gate.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: August 17, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jin-Ping Han, Ramachandran Muralidhar, Dennis M. Newns, Paul M. Solomon
  • Patent number: 11088192
    Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip (IC) structure. The method may be performed by forming a first integrated chip die having one or more semiconductor devices within a first substrate, and forming a passivation layer over the first integrated chip die. The passivation layer is selectively etched to form interior sidewalls defining a first opening, and a conductive material is deposited over the passivation layer and within the first opening. The conductive material is patterned to define a conductive blocking structure that laterally extends past the one or more semiconductor devices in opposing directions. The first integrated chip die is bonded to a second integrated chip die having an array of image sensing elements within a second substrate.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ying Ho, Ching-Chun Wang, Dun-Nian Yaung, Feng-Chi Hung, Yan-Chih Lu
  • Patent number: 11088092
    Abstract: The present disclosure relates to a method of forming an integrated chip. The method may be performed by forming first and second source regions within a substrate. The first and second source regions are separated by a drain region along a first direction. First and second middle-end-of-the-line (MEOL) structures are formed over the substrate. The first and second MEOL structures have bottom surfaces that continually extend past edges of the first and second source regions, respectively, along a second direction perpendicular to the first direction. A power rail is formed that is electrically coupled to the first and second MEOL structures. The power rail has a first interconnect wire, a via rail on and in contact with the first interconnect wire, and a second interconnect wire on and in contact with the via rail. The via rail continuously extends along the first direction past the first and second MEOL structures.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kam-Tou Sio, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Chi-Yeh Yu, Jiann-Tyng Tzeng, Ru-Gun Liu, Wen-Hao Chen
  • Patent number: 11081291
    Abstract: A photosensor includes a first electrode, a second electrode that opposes the first electrode, and a photoelectric conversion layer that is disposed between the first electrode and the second electrode and converts incident light into electric charges. At least one electrode selected from the group consisting of the first electrode and the second electrode is light-transmissive. The photoelectric conversion layer contains a perovskite compound. The fluorescence spectrum of the perovskite compound has a first peak at a first wavelength and a second peak at a second wavelength that is longer than the first wavelength. The photoelectric conversion layer is in ohmic contact with each of the first electrode and the second electrode.
    Type: Grant
    Filed: July 14, 2018
    Date of Patent: August 3, 2021
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Michio Suzuka, Ryuusuke Uchida, Taisuke Matsui
  • Patent number: 11069800
    Abstract: A semiconductor device includes a single electron transistor (SET) having an island region, a bottom source/drain region under the island region, and a top source/drain region over the island region, a first gap between the bottom source/drain region and the island region, a second gap between the top source/drain region and the island region, and a gate structure on a side of the island region.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: July 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 11063005
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first conductive interconnect wire extending in a first direction over a substrate. A second conductive interconnect wire is arranged over the first conductive interconnect wire. A via rail is configured to electrically couple the first conductive interconnect wire and the second conductive interconnect wire. The first conductive interconnect wire and the second conductive interconnect wire extend as continuous structures past one or more sides of the via rail.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kam-Tou Sio, Chih-Ming Lai, Chun-Kuang Chen, Chih-Liang Chen, Charles Chew-Yuen Young, Chi-Yeh Yu, Jiann-Tyng Tzeng, Ru-Gun Liu, Wen-Hao Chen
  • Patent number: 11063237
    Abstract: A flexible organic light-emitting display device includes a display panel which displays an image with light, including: an organic light-emitting device which emits the light; and a plurality of organic layers stacked around the organic light-emitting device, a portion of the plurality of organic layers being exposed outside the display panel, and a metal oxide layer on the display panel, the metal oxide layer contacting the portions of the plurality of organic layers exposed outside the display panel.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: July 13, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sooyoun Kim, Seunghun Kim, Wooyong Sung, Seungyong Song, Taehoon Yang
  • Patent number: 11038010
    Abstract: A structure includes a semiconductor substrate, a conductor-insulator-conductor capacitor. The conductor-insulator-conductor capacitor is disposed on the semiconductor substrate and includes a first conductor, a nitrogenous dielectric layer and a second conductor. The nitrogenous dielectric layer is disposed on the first conductor and the second conductor is disposed on the nitrogenous dielectric layer.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Jian-Shiou Huang, Chia-Shiung Tsai, Cheng-Yuan Tsai, Hsing-Lien Lin, Yao-Wen Chang
  • Patent number: 11018085
    Abstract: A semiconductor device includes a first lower line and a second lower line on a substrate, the first and second lower lines extending in a first direction, being adjacent to each other, and being spaced apart along a second direction, orthogonal the first direction, an airgap between the first and second lower lines and spaced therefrom along the second direction, a first insulating spacer on a side wall of the first lower line facing the second lower line, wherein a distance from the first airgap to the first lower line along the second direction is equal to or greater than an overlay specification of a design rule of the semiconductor device, and a second insulating spacer between the airgap and the second lower line.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: May 25, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Naoya Inoue, Dong Won Kim, Young Woo Cho, Ji Won Kang, Song Yi Han
  • Patent number: 11011462
    Abstract: The present disclosure relates to a semiconductor device. A fuse layer is arranged within a first dielectric layer. A bond pad is arranged on the first dielectric layer. A second dielectric layer is arranged along sidewall and upper surfaces of the bond pad. A passivation layer is arranged over the first and second dielectric layers, and the passivation layer having a bond pad opening overlying the bond pad and a fuse opening overlying the fuse layer. The bond pad has a bottom surface that is co-planar with a bottom surface of the passivation layer.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Chun-Yi Yang, Chih-Hao Lin, Hong-Seng Shue, Ruei-Hung Jang
  • Patent number: 11011613
    Abstract: The present invention provides a flexible substrate with a high dielectric-constant film and a manufacturing method thereof. The manufacturing method comprises following steps: providing a flexible substrate; forming a polysilicon layer on the flexible substrate; coating an HfAlOx solution on the polysilicon layer and forming an HfAlOx insulating layer by baking or annealing the HfAlOx solution; forming a metal gate electrode on the HfAlOx insulating layer; and doping and activating the polysilicon layer to form a source/drain electrode. The metal gate electrode is spaced apart from the source/drain electrode by the HfAlOx insulating layer.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: May 18, 2021
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Peng Jin
  • Patent number: 11004726
    Abstract: A stack of sacrificial layers is formed in a set of N levels. A first etch-trim mask having spaced apart first and second open etch regions is formed over the set. Two levels are etched through using the first etch-trim mask in each of M etch-trim cycles, where M is (N?1)/2 when N is odd and (N/2)?1 when N is even. One level is etched through using the first etch-trim mask in one etch-trim cycle when N is even. The first etch-trim mask is trimmed to increase the size of the first and second open etch regions, in each of etch-trim cycles C(i) for i going from 1 to T?1, where T is (N?1)/2 when N is odd and N/2 when N is even. A second etch mask is formed over the set, covering one of the open etch regions. One level is etched through using the second etch mask.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: May 11, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Yu-Wei Jiang, Jia-Rong Chiou