Abstract: High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a first doped region and a second doped region disposed in a substrate. The first doped region and the second doped region are oppositely doped and adjacently disposed in the substrate. A first isolation structure and a second isolation structure are disposed over the substrate, such that each are disposed at least partially over the first doped region. The first isolation structure is spaced apart from the second isolation structure. A resistor is disposed over a portion of the first isolation structure and electrically coupled to the first doped region. A field plate disposed over a portion of the second doped region and electrically coupled to the second doped region.

Abstract: A method of fabricating a symmetric element of a resistive processing unit (RPU) includes forming a substrate with a channel region connecting two doped regions, and forming a source above one of the two doped regions and a drain above the other of the two doped regions. A gate is formed above the channel region, and a bar ferroelectric is disposed above the channel region and below the gate.

Abstract: Example embodiments relate to a graphene device, methods of manufacturing and operating the same, and an electronic apparatus including the graphene device. The graphene device is a multifunctional device. The graphene device may include a graphene layer and a functional material layer. The graphene device may have a function of at least one of a memory device, a piezoelectric device, and an optoelectronic device within the structure of a switching device/electronic device. The functional material layer may include at least one of a resistance change material, a phase change material, a ferroelectric material, a multiferroic material, multistable molecules, a piezoelectric material, a light emission material, and a photoactive material.

Abstract: The present invention is notably directed to an electro-optical device. The latter comprises a layer structure with: a silicon substrate; a buried oxide layer over the silicon substrate; a tapered silicon waveguide core over the buried oxide layer, the silicon waveguide core cladded by a first cladding structure; a bonding layer over the first cladding structure; and a stack of III-V semiconductor gain materials on the bonding layer, the stack of III-V semiconductor gain materials cladded by a second cladding structure. The layer structure is configured to optically couple radiation between the stack of III-V semiconductor gain materials and the tapered silicon waveguide core. The first cladding structure comprises a material having: a refractive index that is larger than 1.54 for said radiation; and a bandgap, which, in energy units, is larger than an average energy of said radiation.

Abstract: Structures for a cascode integrated circuit and methods of forming such structures. A field-effect transistor of the structure includes a gate electrode finger, a first source/drain region, and a second source/drain region. A bipolar junction transistor of the structure includes a first terminal, a base layer with an intrinsic base portion arranged on the first terminal, and a second terminal that includes one or more fingers arranged on the intrinsic base portion of the base layer. The intrinsic base portion of the base layer is arranged in a vertical direction between the first terminal and the second terminal. The first source/drain region is coupled with the first terminal, and the first source/drain region at least partially surrounds the bipolar junction transistor.

Abstract: A method of fabricating a semiconductor structure includes forming a plurality of semiconductor fins disposed on a semiconductor substrate, wherein at least one of the fins is an unwanted fin including a semiconductor material; providing a conformal protective layer over the plurality of semiconductor fins; forming a mask having an opening over the unwanted fin; removing a portion of the unwanted fin to expose a fin spike; oxidizing the fin spike to form an oxidized semiconductor material; and removing the oxidized semiconductor material to expose a fin base.

Abstract: Display systems and related methods involving bus lines with low capacitance cross-over structures are provided. A representative display system includes: a first structure comprising: a plurality of scan lines extending in a first direction; and a plurality of data lines extending in a second direction and crossing over the scan lines at respective cross-over locations, each of the plurality of data lines having a pair of side walls spaced apart from each other at each of the cross-over locations, with each of the side walls exhibiting a height higher than portions of the data lines not located at the cross-over locations.

Abstract: A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel.

Abstract: A vertical power semiconductor component includes a semiconductor chip, the semiconductor chip having a top main surface and a bottom main surface. Each of said top main surface and said bottom main surface is in a heat exchanging relationship with a top metallization layer and a bottom metallization each of which serving as a heat sink. Each of said top metallization layer and said bottom metallization layer have a layer thickness of at least 15 ?m and have a specific heat capacity per volume that is at least a factor of 1.3 higher than the specific heat capacity per volume of the semiconductor chip. Each of said top metallization layer and said bottom metallization layer serving as a heat sink contacts the respective main surface via a respective diffusion barrier layer.

Abstract: The present disclosure relates to an integrated circuit having a via rail that prevents reliability concerns such as electro-migration. In some embodiments, the integrated circuit has a first plurality of conductive contacts arranged over a semiconductor substrate. A first metal interconnect wire is arranged over the first plurality of conductive contacts, and a second metal interconnect wire is arranged over the first metal interconnect wire. A via rail is arranged over the first metal interconnect wire and electrically couples the first metal interconnect wire and the second metal interconnect wire. The via rail has a length that continuously extends over two or more of the plurality of conductive contacts. The length of via rail provides for an increased cross-sectional area both between the first metal interconnect wire and the second metal interconnect wire and along a length of the via rail, thereby mitigating electro-migration within the integrated circuit.

Abstract: A semiconductor device includes a first circuit 1 and a second circuit 2 that are connected in series, a first terminal T1 that applies a first potential to a first power supply line DL1 of the first circuit 1, a second terminal T2 that applies a second potential to a second power supply line DL2 of the second circuit 2, a third terminal T3 that is connected to a signal transfer line of the first circuit 1, and a protection circuit that is connected to the third terminal T3, and discharges a current from the third terminal T3 to a fourth terminal T4 when a potential of the third terminal T3 becomes higher than a first threshold value. The first power supply line DL1 and the second power supply line DL2 are separated, and the fourth terminal T4 is not directly connected to the first power supply line DL1 and is electrically connected to a lead.

Abstract: A liquid crystal display device includes a gate line in a first direction, a data line in a second direction intersecting the first direction, a pixel including a first region having a transistor connected to the gate and data lines, and a contact hole connecting the transistor to a pixel electrode, and a second region having the pixel electrode, wherein a length of a first width along the first direction on the first region is longer than a length of a second width along the second direction on the first region, and wherein a length of a third width along the first direction on the second region is longer than a length of a fourth width along the second direction on the second region.

Abstract: A memory device includes a cell region and a peripheral circuit region adjacent the cell region. A plurality of gate electrode layers and insulating layers are stacked on the substrate in the cell region, and a plurality of circuit devices are in the peripheral circuit region. A first interlayer insulating layer is on the substrate in the peripheral circuit region and covers the plurality of circuit devices, and a second interlayer insulating layer is on the substrate in the cell region and the peripheral circuit region. A blocking layer is on the plurality of circuit devices between the first and second interlayer insulating layers. The blocking layer is on an upper surface, of the first interlayer insulating layer, and a side surface of the blocking layer is covered by the second interlayer insulating layer.

Abstract: A semiconductor device includes a pair of line patterns disposed on a substrate. A contact plug is disposed between the pair of line patterns and an air gap is disposed between the contact plug and the line patterns. A landing pad extends from a top end of the contact plug to cover a first part of the air gap and an insulating layer is disposed on a second part of the air gap, which is not covered by the landing pad.

Abstract: According to one embodiment, the insulating film is provided between the anode region and the cathode region in the surface of the second semiconductor region. The third semiconductor region is provided inside the second semiconductor region. The third semiconductor region covers a corner of the insulating film on the anode region side. The first electrode contacts the anode region and the third semiconductor region. The second electrode contacts the cathode region. The third electrode is provided on the insulating film and positioned on a p-n junction between the second semiconductor region and the third semiconductor region.

Abstract: A top-emission organic light-emitting display device includes a plurality of pixels each having color filters. Each of the plurality of pixels comprises a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. The first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are arranged sequentially in a column direction. Each of the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel is extended in a row direction rather than in the column direction.

Abstract: In one embodiment, a trench Schottky rectifier includes a termination trench and active trenches provided in a semiconductor layer. A first active trench is configured to be at a shallower depth than the termination trench to provide a trench depth difference. A second active trench is configured to be at a depth similar to the termination trench. The selected trench depth difference in combination with one or more of the other second active trench depth, the dopant concentration of the semiconductor layer, the thickness of the semiconductor layer, first active trench width to termination trench width, and/or dopant profile of the semiconductor layer provide a semiconductor device having improved performance characteristics.

Abstract: An object of the present invention to provide a highly reliable semiconductor device. Another object is to provide a manufacturing method of a highly reliable semiconductor device. Still another object is to provide a semiconductor device having low power consumption. Yet another object is to provide a manufacturing method of a semiconductor device having low power consumption. Furthermore, another object is to provide a semiconductor device which can be manufactured with high mass productivity. Another object is to provide a manufacturing method of a semiconductor device which can be manufactured with high mass productivity. An impurity remaining in an oxide semiconductor layer is removed so that the oxide semiconductor layer is purified to have an extremely high purity. Specifically, after adding a halogen element into the oxide semiconductor layer, heat treatment is performed to remove an impurity from the oxide semiconductor layer. The halogen element is preferably fluorine.

Abstract: A semiconductor device includes a single electron transistor (SET) having an island region, a bottom source/drain region under the island region, and a top source/drain region over the island region, a first gap between the bottom source/drain region and the island region, a second gap between the top source/drain region and the island region, and a gate structure on a side of the island region.

Abstract: A silicon carbide semiconductor device includes: a substrate; a drift layer over the substrate; a base region over the drift layer; multiple source regions over an upper layer portion of the base region; a contact region over the upper layer portion of the base region between opposing source regions; multiple trenches from a surface of each source region to a depth deeper than the base region; a gate electrode on a gate insulating film in each trench; a source electrode electrically connected to the source regions and the contact region; a drain electrode over a rear surface of the substrate; and multiple electric field relaxation layers in the drift layer between adjacent trenches. Each electric field relaxation layer includes: a first region at a position deeper than the trenches; and a second region from a surface of the drift layer to the first region.