Abstract: Multicast data in a wireless network is encoded with FEC codes where K information symbols are encoded into N transmission symbols, N>K, where K−N represents redundancy, such that reception and decoding of any K+A transmission symbols is sufficient to recover the K information symbols, where A is small relative to K. The level of redundancy may be selected to provide adequate performance to a mobile terminal at the edge of a cell, or to the mobile terminal reporting the lowest quality link. Upon handoff, a mobile terminal may be directed to an ongoing multicast in the new cell of the same information, or alternatively the new cell may transmit only the multicast packets the mobile terminal has not received. Different time segments of the information may be separately encoded, or the same information encoded with different level of redundancy, and the encoded data transmitted on different wireless channels.

Abstract: A device for compensating for the nonlinearity of a power amplifier which has a simple configuration and can precisely linearize the transfer characteristics of the power amplifier by predistorting an input signal of the power amplifier. The nonlinearity compensation device of the present invention converts an RF input signal into an IF band rather than a baseband and predistorts the RF input signal in digital domain, and thus any modulation or demodulation process is obviated and the simultaneous processing of signals in multiple channels is facilitated. A first downconverter receives the RF input signal and converts the frequency band of the signal into the IF band to output an IF input signal. A predistortion unit receives and predistorts the IF input signal to compensate for the nonlinearity, and outputs an IF predistorted signal. An upconverter converts the frequency band of the IF predistorted signal into the RF band to provide such a signal to the amplifier.

Abstract: A circuit, apparatus and method for efficiently and accurately calibrating an output driver current are provided in embodiments of the present invention. In an embodiment of the present invention, a circuit comprises a first digital-to-analog converter (“DAC”) that generates a first current. A first transistor is coupled to the first DAC and generates a first biasing current responsive to the first current. A second DAC is coupled to the first transistor and generates a first control current responsive to the first biasing current. According to an embodiment of the present invention, the first and second DACs are binary weighted control DACs. According to an embodiment of the present invention, the binary weighted values of the second DAC are obtained in response to a calibration signal generated by a controller. According to an embodiment of the present invention, the first DAC is an M-bit DAC and the second DAC is an N-bit DAC, wherein M is less than N.

Abstract: A miniaturized phase shifter and a multi-bit phase shifter are provided, in which filters are constructed using capacitors at FET pinch-off and pass phase can be shifted by turning the FET on and off, the phase shifter including: a first FET having a drain electrode connected to an input terminal and a source electrode connected to an output terminal; a second FET, in which one of a drain electrode and a source electrode thereof is connected to the source electrode of the first FET and the other is connected to ground via a first inductor; and a third FET, in which one of a drain electrode and a source electrode thereof is connected to the drain electrode of the first FET and the other is connected to ground via a second inductor.

Abstract: Apparatuses and methods for decoding a bit stream of variable-length and fixed-length codewords representing encoded digital content. A decoder includes a memory for storing microinstructions that control the decoder. The decoder further includes a first barrel shifter for extracting a first bit field from the bit stream, a position of the first bit field being specified by the microinstruction, and a second barrel shifter for extracting a second bit field from the bit stream, a position of the second bit field being specified by the microinstructions. A microprogram counter keeps an address of a currently-executing microinstruction of the microinstructions, where a next state of the microprogram counter is determined by the microinstructions and the first bit field. A data converter modifies a value of the second bit field according to the microinstructions. A data storage stores either data in the microinstructions or an output of the data converter as decoded data values.

Abstract: Systems and methods that encode and decode data in a manner that limits error propagation by parsing a data word of length n into a predetermined number of data blocks, individually encoding each data block into a single associated code block, and then combining each of the code blocks to form a resulting code word of length (n+1), resulting in a code rate of n/(n+1). By parsing and encoding the data word in this manner, errors that occur with respect to one or more bits of one code block will not be propagated throughout an entire data word during the decoding process.

Abstract: A dynamic range on demand radio frequency (RF) receiver (300) includes a wideband detector (303), off-channel detector (313) and on-channel detector (327) supplying input to an automatic gain control (307) for adjusting a dynamic control stage to control dynamic range and resolution of digital baseband signals (329, 331).

Abstract: A combination of pre-distortion and post-distortion processes compensate for errors in I/Q channel orthogonality. The pre-distortion and post-distortion processes are calibrated to compensate for these errors at a variety of frequencies across a frequency span, thereby providing frequency-dependent compensation for I/Q channel mismatch. Pre-distortion calibration is effected by coupling the filtered analog I/Q modulated signals from the transmitter of a wireless transceiver directly to the analog-to-digital converters of the receiver of the wireless transceiver. Coupling the analog I/Q modulated signals from the transmitter directly to the channel filters that precede the analog-to-digital converters of the receiver effects post-distortion calibration.

Abstract: Methods and apparatus are provided for use in digital information processors that support digital memory buffers. In one aspect of the present invention, a digital signal processor receives a swap instruction and responds to the swap instruction by swapping the contents of a first address register and a second address register. In another aspect, a digital signal processor receives a swap instruction, swaps the contents of a first address register and a second address register in a future file, generates and sends one or more control signals to an architecture file in a downstream stage of a pipeline in response to the swap instruction, and swaps the contents of the first address register and the second address register in the architecture file in response to the one or more control signals.

Abstract: A delta-sigma modulator for an analog-to-digital converter device and method for reducing a quantization error resulting from differences between the periods of the delta-sigma quantizer clock and the counter clock by using a pulse-width modulator in which the timing of the rising edge of each pulse is controlled by a relatively low-frequency clock signal, and the trailing edge of each pulse is controlled by the input analog signal level. Accordingly, the device and method are particularly effective for measuring the duty cycle of a pulse train from a delta-sigma analog-to-digital converter device when it is undesirable to run the high-frequency clock signal between the pulse-width modulator and the counter, for example when significant physical separation between the delta-sigma modulator and the counter.

Abstract: A device and method for driving a capacitive load that has a more power efficient design. The power efficient capacitive load driving device can be used to drive one or more acoustic transducers of a parametric audio system with low distortion and a flat frequency response. The capacitive load driving device includes a current source, a plurality of switches interconnected in an “H-bridge” configuration coupled to an output of the current source, and a controller. The plurality of interconnected switches is coupleable to at least one capacitive load. By driving the capacitive load with at least one controlled switched drive signal, the capacitive load driving device delivers (recovers) energy to (from) the capacitive load in an optimal manner, thereby generating a desired output voltage waveform across the capacitive load with increased power efficiency.

Abstract: A potentiometer and logic circuitry attached to a common substrate. In one aspect the potentiometer and logic circuitry is an integrated potentiometer mounted on an upper surface of a circuit board with circuitry on a lower surface of the circuit board. The circuitry conducts the position and movement of the potentiometer into potentiometer output signals.

Abstract: To provide a mixer/amplifier capable of providing variable gain while maintaining a substantially constant common mode operating voltage level and to maintain a substantially constant operating voltage in new, low voltage designs and to provide a mixer/amplifier in low-power direct conversion receiver. A low noise amplifier is provided in which a gain control signal is provided through a differential current source. Two output currents I1 and I2 are provided. I1+I2=a constant. I1 and I2 are mirrored in first and second paths, one including amplifier transistors and optionally a Gilbert cell multiplier. Irrespective of amplifier gain, the current through the two paths remains equal to I1 and I2, and common mode voltage remains constant.

Abstract: An A/D converter arrangement comprises an A/D converter (6) to which analog signals from a plurality of signal channels (2) can be fed for A/D conversion. With the help of an appropriate control means (8), converter parameters of the A/D converter (6) or even other operating parameters of the A/D converter arrangement, such as certain functions performed in response to an A/D conversion which has been carried out for example, are set in a channel-specific way as a function of the signal channel (2) which is to be converted at the time.

Abstract: For “Super Audio CD” (SACD) the DSD signals are losslessly coded, using framing, prediction and entropy coding. Besides the efficiently encoded signals, a large number of parameters, i.e. the side-information, has to be stored on the SACD too. The smaller the storage capacity that is required for the side-information, the better the overall coding gain is. Therefore coding techniques are applied to the side-information too so as to compress the amount of data of the side information.

Abstract: A system and method to perform context-adaptive variable length decoding (CAVLC) of transform coefficient levels for block-based motion-compensated decoding of moving pictures, corresponding to transform coefficients. The system and method includes complexity-reduction improvements in the coefficient level decoding process, such as simplified and extended range of Lev-VLC tables. Specifically, the number of Lev-VLC tables is extended from 5 to 7 and only 1 escape code (28-bit escape code) is used for tables Lev-VLC1to Lev-VLC6. The system and method also includes a simplified and improved table selection process. The table selection for the first Coefficient_level after trailing ones depends on total number of non-zero coefficients and number of trailing ones which are local variables within the CAVLC module.

Abstract: A nested chopper circuit includes a first chopper section, which is coupled to input terminals and is controlled by a pair of non-overlapping clocks, and a second chopper section, which is coupled to the first chopper section and is controlled by a pair of chopper clocks. The pair of non-overlapping clocks is a multiple of the pair of chopper clocks, and the non-overlapping clocks are configured to invert on a period continuously. When the pair of chopper clocks (&phgr;11 and &phgr;12) controls switches S1, S2, S3, and S4 of the second section, these switches follow the following logic when operated in conjunction with the pair of non-overlapping clocks (&phgr;A and &phgr;B): switches S1 & S4: &phgr;A·&phgr;11+&phgr;B·&phgr;12; and switches S2 & S3: &phgr;A·&phgr;12+&phgr;B·&phgr;11. A method for chopping an analog input signal for sampling also is described.

Abstract: A way of converting digital signals to analog signals is provided for wireless communications. An apparatus is provided that comprises a resistive-ladder array to convert a first portion of a digital input signal to a first analog output signal. The apparatus further includes a current-mode array to convert a second portion of the digital input signal to a second analog output signal.

Abstract: An apparatus, a method and a system to efficiently manipulate in the compressed domain, spatial and/or temporal scaling of matching pursuit-coded digital signals. These manipulations, referred to as transcoding, may take place at a transcoding proxy located at an origin server, in any intermediary along the transmission path from the origin server to the client device, and/or at the client device. The preferred embodiment focuses on a method to perform rate adaptation and spatio-temporal scaling of a video stream composed of 3-D atoms in order to serve a set of heterogeneous client devices (e.g., a high-end personal computer, a personal digital assistant and a wireless phone). The proposed method applies to 1-D atoms (decomposition of audio signals) and 2-D atoms (image decomposition).

Abstract: A new LZW compressor implementation architecture utilizes a plurality of prefix tables corresponding to respective prefix codes. A string is stored by storing the code associated with the string in a prefix table corresponding to the code of the string prefix at a prefix table location corresponding to the extension character of the string. A search for the longest matching string is performed by determining if the prefix table location is empty corresponding to the currently fetched character in the prefix table associated with the code of the currently matched string. If the location is not empty, it is storing the code of the string comprising the currently matched string extended by the currently fetched character. This string code is used as the next match with which to continue the search with the next fetched character. When the location is empty, the longest match has been determined to be the currently matched string.