Abstract: Parallel analog-to-digital converter systems are provided in which converters are temporally interleaved. In particular, converters are partitioned into at least two converter groups which are assigned different respective group converter periods that are multiples of the system periods. With converters in each of the converter groups, respective samples are processed over that group's respective group converter period and the group converter periods of all converters are temporally shifted to process each of the samples with at least one of the converters.

Abstract: A DAC-based voltage regulator system for a non-volatile memory device comprises a charge pump circuit having an enable input and a voltage output node. A voltage-to-current converter has an input coupled to the voltage output node and an output coupled to a virtual ground node. A current source is coupled to the virtual ground node and sinks one of a plurality of currents in response to states of a plurality of digital input signals. A transconductance amplifier has an inverting input at the virtual ground node, a non-inverting input coupled to a reference voltage potential, and an output. A comparator has a first input coupled to the output of the transconductance amplifier, a second input coupled to a reference voltage potential, and an output coupled to the enable input of said charge pump.

Abstract: A noise shaper including first and second quantizers and first and second feedback paths each providing feedback from a corresponding quantizer output. A loop filter system implements a plurality of transfer functions including a first non-zero transfer function between the first feedback path and an input of the first quantizer, a second non-zero transfer function between the first feedback path and an input of the second quantizer, a third non-zero transfer function between the second feedback path and the input of the first quantizer and a fourth non-zero transfer between the second feedback path and the input the second quantizer.

Abstract: An ultra wideband, frequency dependent attenuator apparatus for providing a loss which can be matched with a physically longer, given delay line, but yet which provides a much shorter time delay than the physically longer, given delay line with constant group delay. The apparatus is formed by an ordinary microstrip transmission line placed in series with an engineered lossy microstrip transmission line, with both transmission lines being placed on a substrate to effectively form a hybrid microstrip transmission line. The lossy transmission line includes resistive material placed along the opposing longitudinal edges thereof. In one embodiment, spaced apart metal tracks are formed along each strip of resistive material to provide the lossy microstrip transmission line with a desired loss characteristic.

Abstract: A semiconductor integrated circuit comprises a digital-to-analogue converter for converting a digital signal into an analogue signal to output an analogue current signal, a current-to-voltage converter for converting the analogue current signal output by the digital-to-analogue converter, into an analogue voltage signal whose level has been controlled, and a filter for filtering the analogue voltage signal converted by the current-to-voltage converter. The current-to-voltage converter converts the current signal into the voltage signal in which a factor variable in accordance with manufacturing process conditions and/or environmental conditions has been corrected.

Abstract: Techniques that may aid in the recovery of clock and data signals include receiving a stream of incoming data signals and determining an offset based, at least in part, on the state of a transition bit sampled from the stream of incoming data signals. The slice level of an input sampling circuit is adjusted based on the offset. Re-timed data signals corresponding to the incoming data signals may be generated.

Abstract: An interface includes an encoder to receive a stream of input symbols and, in response, to output a corresponding stream of output symbols of substantially equal weight via multiple signal lines, which can improve noise/speed performance. The encoder outputs the stream of output symbols so that no output symbol is consecutively repeated. A repeat symbol is used to indicate that the current symbol is identical to the immediately preceding symbol. This encoding allows an interface receiving the stream of output symbols can extract a clock signal from the stream.

Abstract: The present invention relates to a dielectric device that is suitable for miniaturization and height reduction and is surface-mountable. In a resonator unit Q1, a first hole 41 is provided to a dielectric substarate 1, extends from a surface 21 toward a surface 22 opposite thereto, opens in the surface 21, and has a first internal conductor 61 in the interior. A second hole 51 is provided to the dielectric substarate 1, opens in a surface 23 adjacent to the surface 21, extends from the surface 23 toward a surface 24 opposite thereto, and is connected with the first hole 41 in the interior of the dielectric substarate 1. The second hole 51 has a second internal conductor 81 in the interior, and the second internal conductor 81 is connected to the first internal conductor 61 in the interior of the dielectric substarate 1.

Abstract: A method is provided for analog/digital converting of at least one analog low-frequency signal with an analog/digital converter which can detect only an analog signal with a frequency above a predetermined border frequency value, wherein at least one analog low-frequency signal and at least one analog high-frequency signal are provided. An analog intermediate signal is generated from said analog low-frequency signal(s) and said analog high-frequency signal(s) and is input to the analog/digital converter. The analog intermediate signal is converted into a digital intermediate signal, and a digital low-frequency signal corresponding to said analog low-frequency signal is determined from the digital intermediate signal.

Abstract: Current source arrays having a plurality of current sources arranged in an array of columns and rows are disclosed. The outputs of the current sources in even rows of the first column of an array are connected to the output of a current source in each of the other columns located along a first diagonal through the array from the respective current source in the first column. Also the outputs of the current sources in odd rows of the first column of the array are each connected to the output of a current source in each of the other columns located along a second diagonal through the array from the respective current source in the first column, the second diagonals being in an opposite diagonal direction from the first diagonals. When used in a current steering thermometer DAC, preferably but not necessarily, the current sources for the least significant bits are located on a main diagonal of the array.

Abstract: A circuit for generating a pulse-width-modulated signal comprises a phase-locked loop (PLL) having a duty-cycle-insensitive phase comparator and a Sigma-Delta pulse width modulation circuit suitable for providing the voltage-controlled oscillator function of the PLL. Thereby, frequency of the signal generated is synchronized by the PLL to the specified frequency of a synchronization signal, and is thus independent of the duty cycle.

Abstract: An M+N bit DAC includes an N-bit interpolation circuit for interpolating between a first voltage (Vhigh) on a first conductor (17A) and a second voltage (Vlow) on a second conductor (17B), an output amplifier (10), a calibration interpolation circuit (14), a memory circuit (36) for storing error information corresponding to various values of the first voltage and second voltage, outputs of the N-bit interpolation circuit and the calibration interpolation circuit being coupled to inputs of the output amplifier, and switching circuitry responsive to a N-bit portion of a M+N input word coupling the memory to inputs of the of the calibration interpolation circuit so as to correct integral nonlinearity errors associated with the various values of the first and second voltages.

Abstract: The invention provides a dielectric resonator device comprising a coaxial dielectric resonator 2 which comprises a dielectric block 21 having a bore 22 extending therethrough, an outer conductor layer 24 formed on an outer peripheral surface of the dielectric block 21, an inner conductor layer 23 formed on the dielectric block 21 over an inner peripheral surface thereof defining the bore 22, a short-circuiting conductor layer 25 providing a short circuit between the outer conductor layer 24 and the inner conductor layer 23, and a separated conductor layer 3 formed on the outer peripheral surface of the dielectric block 21 and electrically separated from the outer conductor layer 24. The separated conductor layer 3 is connected to the ground by a switch SW, which varies the capacity of the resonator 2 upon switching to alter the resonance frequency thereof.

Abstract: An electronic apparatus with a high inductive reactance for differential signals per unit area and a small inductive reactance for common-mode signals relative to its inductive reactance for differential signals with predictable and scalable characteristics. This may be achieved by configuring transmission line pairs such that currents associated with the differential component of a source signal in the first and second transmission lines are aligned and currents associated with the common mode component of a source signal in the first and second transmission lines are counter-aligned. Advantageously, the current invention may be implemented using currently available technology and integrated into a variety of different devices such as broad-band and narrow-band amplifiers, high-speed logic gates, mixers, oscillators, wireless local area networks, global positioning systems and modern communication systems.

Abstract: A highly efficient analog-to-digital (A/D) converter circuit that converts an external analog signal sequentially generated from an external analog signal source into an n-bit digital data signal (n is an integer equal to or more than two) includes a digital-to-analog (D/A) converter circuit that converts an n-bit digital data signal into an analog signal and outputting the analog signal from a first output terminal, a comparator that compares a signal level of an external analog signal supplied from an external device with a signal level of the analog signal outputted from the first output terminal, and a digital integrator circuit that digitally integrates a 1-bit digital data signal outputted from the comparator and thereby producing an n-bit digital data signal.

Abstract: A system and method that provides a unique or custom context for a plurality of blocks of data, yet compresses the blocks independently from the others, such that each block is independently decompressible. The method analyzes a collection of blocks for compression, and computes a unique context, such as a Huffman tree, given the distribution of symbols or phrases across all the blocks in the collection. Each block in the collection can be independently decompressed, in any order, using the shared context that is common to the collection.

Abstract: A data encoding and decoding system that comprises a composite fixed-variable-length coding process and an offset-difference coding process for improving data compression performance. A composite fixed-variable-length coding process encodes an input data by first comparing the input data to a predetermined threshold, then selecting a coding scheme from two preselected coding schemes and encoding the input data in accordance with the selected coding scheme. The composite fixed-variable-length coding process also generates an identifier to indicate the selected coding scheme to decode the coded output data if a response to comparing the input data with a predetermined threshold differs from a statistically determined response. An offset-difference coding process encodes a paired input data by first determining the greater of the two input data, then calculating the difference between the larger input data and the smaller input data and replacing the larger input data with the calculated difference.

Abstract: A method and apparatus to switch between two audio streams without creating a clicking transient. A first serial audio stream is brought into a serial shift register. A series of samples of that audio stream are multiplied by reducing coefficients until a contribution of the first audio stream reaches zero. Then, a second serial audio stream is brought into the serial shift register. Increasing coefficients are applied to a series of samples until a contribution of the second audio stream is one.

Abstract: A control unit (100) sets up a path in a protocol conversion apparatus (30) based on call setting information from the calling side terminal. A signal monitor unit (300) monitors main data 220a transmitted in the path and sent/received between the terminals. When a specific connectivity confirmation sequence is detected by the signal monitor unit (300), the result is forwarded to the control unit (100). Based on the forwarded result, the control unit (100) specifies a protocol of the calling side terminal and a protocol of the called side terminal. A protocol conversion unit (310) performs the most suitable protocol conversion based on the specified protocols.

Abstract: A controllable attenuator has an input and an output, and comprises a first resistive element, a first capacitor connected in series between the input and the output, a first controllable shunting transistor connected between the output and a supply terminal via a second resistive element, and a controllable bypass transistor connected between the input and the output. The controllable attenuator may form part of a radio receiver circuit, the attenuator being positioned between a matching circuit and a low-noise amplifier.