Patents Examined by John Niebling
  • Patent number: 6913970
    Abstract: A semiconductor device formed by forming contact holes in the insulating film, that covers the source/drain of the MOSFET and the capacitor in the memory cell region, on the lower electrode of the capacitor by the same steps, then filling the plugs into contact holes, and then forming the contact hole on the upper electrode of the capacitor. Accordingly, there can be provided the semiconductor device having the ferroelectric capacitor, capable of simplifying respective wiring connection structures to the upper electrode and the lower electrode of the capacitor by suppressing the damage to the capacitor formed over the transistor.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: July 5, 2005
    Assignee: Fujitsu Limited
    Inventors: Kenichi Inoue, Yoshinori Obata, Takeyasu Saito, Kaoru Saigoh, Naoya Sashida, Koji Tani, Jirou Miura, Tatsuya Yokota, Satoru Mihara, Yukinobu Hikosaka, Yasutaka Ozaki
  • Patent number: 6900859
    Abstract: An in-plane switching mode active matrix liquid crystal display panel includes a substrate structure having a black matrix defining openings and color filter layers disposed in the openings, another substrate structure formed with thin film transistors, pixel electrodes and common electrodes for generating local lateral electric fields and liquid crystal filling the gap between the substrate structures, wherein a highly resistive layer is inserted in the gap between the black matrix and the color filter layers for blocking the color filter layers from electric charges induced in the black matrix due to a potential variation on the pixel electrodes, thereby preventing the visual images from an after image and irregularity in colors.
    Type: Grant
    Filed: October 29, 2001
    Date of Patent: May 31, 2005
    Assignee: NEC LCD Technologies, Ltd.
    Inventor: Kimikazu Matsumoto
  • Patent number: 6864953
    Abstract: An exposure apparatus for performing exposure of patterns of a reticle onto a substrate includes a first housing covering an optics space containing members of an optical system of an optical path of exposing light, a second housing covering a drive space containing driving members, which adjoins the optics space, members transparent to exposing light provided at boundaries of the adjacent first and second housings, a gas supplier which supplies the interior of the first and second housings with a purging gas, pressure sensors which sense pressures inside respective ones of the first and second housings, and a control unit which controls the gas supplier on the basis of outputs from the pressure sensors in such a manner that pressures within the respective first and second housings will attain respective ones of predetermined pressures.
    Type: Grant
    Filed: May 29, 2001
    Date of Patent: March 8, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shigeyuki Uzawa
  • Patent number: 6829045
    Abstract: An audio-visual storage unit having an electronically written display indicating a rental return time.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: December 7, 2004
    Assignee: Eastman Kodak Company
    Inventor: Stanley W. Stephenson
  • Patent number: 6828191
    Abstract: A trench capacitor, in particular for use in a semiconductor memory cell, has a trench formed in a substrate; an insulation collar formed in an upper region of the trench; an optional buried plate in the substrate region serving as a first capacitor plate; a dielectric layer lining the lower region of the trench and the insulation collar as a capacitor dielectric; a conductive second filling material filled into the trench as a second capacitor plate; and a buried contact underneath the surface of the substrate. The substrate has, underneath its surface in the region of the buried contact, a doped region introduced by implantation, plasma doping and/or vapor phase deposition. A tunnel layer, in particular an oxide, nitride or oxinitride layer, is preferably formed at the interface of the buried contact. A method for producing a trench capacitor is also provided.
    Type: Grant
    Filed: July 28, 1999
    Date of Patent: December 7, 2004
    Assignee: Siemens Aktiengesellschaft
    Inventors: Kai Wurster, Martin Schrems, J├╝rgen Faul, Klaus-Dieter Morhard, Alexandra Lamprecht, Odile Dequiedt
  • Patent number: 6819161
    Abstract: The invention provides an apparatus for temporarily isolating a die from other dice on a wafer commonly connected to one or more common conductors. The conductors are connected to each die through a temporary isolation device, such as a diode. The common conductor supplies a signal to all dice during one set of test procedures, while the temporary isolation device can be used to isolate a die from the common conductor during another set of test procedures.
    Type: Grant
    Filed: October 11, 2002
    Date of Patent: November 16, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Phillip E. Byrd, Paul R. Sharratt
  • Patent number: 6812046
    Abstract: One embodiment of the present invention provides a system that electronically aligns pads on different semiconductor chips to facilitate communication between the semiconductor chips through capacitive coupling. The system operates by measuring an alignment between a first chip and a second chip, wherein the first chip is situated face-to-face with the second chip so that transmitter pads on the first chip are capacitively coupled with receiver pads on the second chip. Next, the system uses the measured alignment to associate transmitter pads on the first chip with proximate receiver pads on the second chip. The system then selectively routes data signals to transmitter pads on the first chip so that the data signals are communicated through capacitive coupling to intended receiver pads in the second chip that are proximate to the transmitter pads.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: November 2, 2004
    Assignee: Sun Microsystems Inc.
    Inventors: Robert J. Drost, Ivan E. Sutherland, Gregory M. Papadopoulos
  • Patent number: 6803264
    Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: October 12, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani
  • Patent number: 6800559
    Abstract: Chemical generator and method for generating a chemical species at a point of use such as the chamber of a reactor in which a workpiece such as a semiconductor wafer is to be processed. The species is generated by creating free radicals, and combining the free radicals to form the chemical species at the point of use.
    Type: Grant
    Filed: January 3, 2003
    Date of Patent: October 5, 2004
    Assignee: Ronal Systems Corporation
    Inventor: Ronny Bar-Gadda
  • Patent number: 6798038
    Abstract: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: September 28, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuhiro Sato, Masayuki Ichige, Seiichi Mori, Yuji Takeuchi, Hiroaki Hazama, Yukio Nishiyama, Hirotaka Ogihara, Naruhiko Kaji
  • Patent number: 6794203
    Abstract: The present invention provides a method of producing an added defect count for monitoring the property of chambers or wafers. First, a proper pre-process sensitivity is determined with map to map process by maximizing the summation of a mapping rate and a catching rate. Second, a wafer is scanned with the proper pre-process sensitivity and a pre-process particle number P1 is recorded. Third, a manufacturing step is processed on the wafer. Fourth, the wafer is scanned with the most sensitive scale of the post-process sensitivities and a post-process particle number P2 is recorded. Finally, the post-process particle number P2 is subtracted from the pre-process particle number P1.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: September 21, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Wei-Ming Chen, Kun-Yu Liu, Chun-Chieh Chen, Lien-Che Ho
  • Patent number: 6788368
    Abstract: The reflective liquid crystal display device comprises a polarizing plate disposed forwardly of a liquid crystal cell, a relector which is disposed on backside of the liquid crystal cell and reflects an incident light, and a light-scattering sheet which is disposed forwardly of the reflector and scatters the incident light isotopically. The light-scattering sheet can be prepared with the use of a spinodal decomposition method of coating a mixture liquid containing a plurality of polymers varying in refractive index on a transparent support and evaporating or removing a solvent to form a light-scattering layer having a droplet phase structure. The light-scattering layer includes a light-scattering layer showing a maximum intensity of the scattered-light at scattering angles of 3 to 40°, and a light-scattering layer showing maximums intensity of the scattered-light respectively at smaller angles of 2 to 2° and larger angle &thgr;b.
    Type: Grant
    Filed: November 23, 2001
    Date of Patent: September 7, 2004
    Assignee: Daicel Chemical Industries, Ltd.
    Inventors: Hiroshi Takahashi, Yoshiyuki Nishida, Masaya Omura, Shuji Nakatsuka
  • Patent number: 6784106
    Abstract: A method for drying a semiconductor substrate includes the steps of clearing the substrate by supplying a liquid into a processing bath of a chamber, injecting first dry gases onto a surface of the supplied liquid, draining the liquid from the processing bath so that the substrate is slowly exposed to the surface of the liquid, and injecting a second dry gas into the chamber and forcibly exhausting gas in the chamber.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: August 31, 2004
    Assignee: DNS Korea Co., Ltd
    Inventors: Jeong-Yong Bae, Chang-Ro Yoon, Pyeng-Jae Park
  • Patent number: 6780687
    Abstract: Protrusions called ridges are formed on the surface of a crystalline semiconductor film formed by a laser crystallization method or the like. A heat absorbing layer are formed below a semiconductor film. When the semiconductor film is crystallized by laser, a temperature difference is produced between a semiconductor film 1010 positioned above a heat absorbing layer 1011 and a semiconductor film 1013 of the other region to produce a difference in thermal expansion at the boundary of the outside end 1015 of the heat absorbing layer. This difference produces a strain to form a surface wave. The surface wave starting at the outer periphery of the heat absorbing layer is formed in the vicinity of the heat absorbing layer. When the semiconductor layer is solidified after it is melted, the protrusions of the surface wave remain as protrusions after the semiconductor film is solidified.
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: August 24, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Setsuo Nakajima, Ritsuko Kawasaki
  • Patent number: 6776850
    Abstract: A preventive maintenance tool which may be installed on a metal chemical vapor deposition (CVD) chamber to prevent escape of contaminating and toxic gases from the chamber interior during preventative maintenance (PM) cleaning of the chamber. The tool comprises a cylindrical tool body which fits to the lid O-ring of the chamber to form a gas-tight seal therewith; a vacuum line connector nipple extending from the body for connection to a vacuum line; and a lid panel rotatably mounted in the body and fitted with a pair of hinged closing panels for reversibly sealing the chamber and facilitating chamber cleaning.
    Type: Grant
    Filed: June 8, 2002
    Date of Patent: August 17, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Miao-Cheng Liao, Ying-Lang Wang, Hung-Hsin Liang, Hsiang-Sheng Cheng, Sheng-Te Shu, Chih-Yuan Yang
  • Patent number: 6773935
    Abstract: A confocal three dimensional inspection system, and process for use thereof, allows for rapid inspecting of bumps and other three dimensional (3D) features on wafers, other semiconductor substrates and other large format micro topographies. The sensor eliminates out of focus light using a confocal principal to create a narrow depth response in the micron range.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: August 10, 2004
    Assignee: August Technology Corp.
    Inventors: Cory Watkins, David Vaughnn, Alan Blair
  • Patent number: 6770958
    Abstract: An under bump metallurgy (UBM) structure is described. Two UBM mask processes are utilized. First, a top layer of copper (Cu) and/or a middle layer of nickel-vanadium (NiV) or chrome-copper (CrCu) is personalized by standard photoprocessing and etching steps utilizing a bump based size mask. This is followed by patterning an underlying seed layer with a second, larger mask, thereby preventing damage to the aluminum cap and seed layer undercut during the etching process.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: August 3, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chung Yu Wang, Chender Huang, Pei-Haw Tsao, Ken Chen, Hank Huang
  • Patent number: 6756281
    Abstract: A semiconductor device and method of fabricating the device. An emitter region is formed self centered and self aligned symmetrically with a base region. Using frontside processing techniques, a collector is formed symmetrically self-aligned with the base region and the emitter region. The collector region may be further formed self-centered with the base region using backside processing techniques. The self-aligned and self-centered symmetric structure virtually eliminates parasitic elements in the device significantly improving the device performance. The device is scalable on the order of approximately 0.1 microns. The method also provides reproduceability and repeatability of device characteristics necessary for commercial manufacture of the symmetric device.
    Type: Grant
    Filed: March 14, 2002
    Date of Patent: June 29, 2004
    Assignee: Ziptronix
    Inventor: Paul Enquist
  • Patent number: 6753196
    Abstract: An electron source 10 has an n-type silicon substrate 1, a drift layer 6 formed on one surface of the substrate 1, and a surface electrode 7 formed on the drift layer 6. A voltage is applied so that the surface electrode 7 becomes positive in polarity relevant to the substrate 1, whereby electrons injected from the substrate 1 into the drift layer 6 drift within the drift layer 6, and are emitted through the surface electrode 7. In a process for manufacturing this electron source 10, when the drift layer 6 is formed, a porous semiconductor layer containing a semiconductor nanocrystal is formed in accordance with anodic oxidation. Then, an insulating film is formed on the surface of each semiconductor nanocrystal. Anodic oxidation is carried out while emitting light that essentially contains a wavelength in a visible light region relevant to the semiconductor layer.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: June 22, 2004
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Takuya Komoda, Tsutomu Ichihara, Koichi Aizawa, Yoshiaki Honda, Yoshifumi Watabe, Takashi Hatai, Toru Baba
  • Patent number: 6746911
    Abstract: Disclosed are a semiconductor device and a method for fabricating the same and, more particularly, a method for decreasing the size of semiconductor devices by stacking two substrates, one of which has only memory cells and the other of which has only logic circuits is disclosed. The disclosed method includes forming memory cells on a first semiconductor substrate; forming logic circuits on a second semiconductor substrate; and stacking the second semiconductor substrate on the first semiconductor substrate in order that the memory cells are electrically operable to the logic circuits on the second semiconductor substrate. In the disclosed stacked semiconductor substrate, the logic circuit area is placed on the memory cell area and these two areas are electrically connected by a metal interconnection, thereby decreasing the size of the semiconductor devices.
    Type: Grant
    Filed: May 22, 2003
    Date of Patent: June 8, 2004
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Il-Suk Han