Abstract: Integrated circuit (IC) devices include a metal-insulator-metal (MIM) capacitor having a top electrode plate, a bottom electrode plate, and a plurality of intermediate electrode plates between the top electrode plate and the bottom electrode plate. A plurality of dielectric layers may separate each of the electrode plates of the MIM capacitor from adjacent plates of the MIM capacitor. Each of the intermediate electrode plates may have a thickness that is greater than a thickness of the top electrode plate and the bottom electrode plate. By providing multiple intermediate electrode plates between the top and bottom electrode plates of the MIM capacitor, and allocating the greatest plate thicknesses to the intermediate plates, the capacitance density may be increased in a given area of the IC device, which may provide increased performance for the IC device.

Abstract: One or more embodiments of the present disclosure are directed toward improved methods of fabricating a semiconductor device utilizing multi-level electron beam lithography (e-beam lithography), an alignment marker for multi-level e-beam lithography, and a semiconductor device including the alignment marker. A method of fabricating a semiconductor device may include: forming an alignment marker in a substrate, the alignment marker including tantalum; determining, utilizing a backscatter electron detector of an electron beam lithography tool, a location of an edge of the alignment marker based on an atomic number contrast between the alignment marker and the substrate; and forming, utilizing the electron beam lithography tool, at least one transistor in the substrate based on the location of the edge of the alignment marker.

Abstract: Embodiments of a method of forming one or more holes in a substrate for use as a process chamber component are provided herein. In some embodiments, a method of forming one or more holes in a substrate for use as a process chamber component include forming the one or more holes in the substrate with one or more laser drills using at least one of a percussion drilling, a trepanning, or an ablation process, wherein each of the one or more holes have an aspect ratio of about 1:1 to about 50:1, and wherein the substrate is a component for gas delivery or fluid delivery.

Abstract: A method for manufacturing a display device includes preparing a display panel that includes a first area, a bending area extending from the first area, and a second area extending from the bending area, attaching an anti-reflection layer to the display panel, removing a first removal section of a first releasing film disposed on the anti-reflection layer, the first removal section overlapping the second area of the display panel in a plan view, and providing a cover tape onto a first section of the anti-reflection layer that overlaps the second area of the display panel in a plan view.

Abstract: A semiconductor device having favorable electrical characteristics is provided. A semiconductor device having stable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, and a first conductive layer. The semiconductor layer includes an island-shaped top surface. The first insulating layer is provided in contact with a top surface and a side surface of the semiconductor layer. The first conductive layer is positioned over the first insulating layer and includes a portion overlapping with the semiconductor layer. In addition, the semiconductor layer includes a metal oxide, and the first insulating layer includes an oxide. The semiconductor layer includes a first region overlapping with the first conductive layer and a second region not overlapping with the first conductive layer.

Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

Abstract: A semiconductor structure includes a substrate, bit line structures, and capacitor connection lines. A plurality of bit line structures are arranged on the substrate. Contact holes are formed between adjacent bit line structures. A capacitor connection line includes a first conductive block and a second conductive block. The first conductive block and the second conductive block are sequentially filled in a contact hole. A chamfered structure is formed on a top end of the first conductive block. The chamfered structure is adjacent to a bit line structure. A bottom end of the second conductive block matches the chambered structure.

Abstract: A gas ring is attached to an upper portion of a chamber side portion as a side wall of a chamber. The gas ring is formed by overlapping an upper ring and a lower ring. A gap between the upper ring and the lower ring provides a flow path for processing gas. A labyrinthine resisting unit is formed in the flow path. The mass of the lower ring having an inner wall surface is increased to increase heat capacity. The lower ring is attached to the chamber side portion to be in surface contact with the chamber side portion, so that thermal conductivity from the lower ring to the chamber side portion has a large value, and the amount of heat accumulated in the lower ring is reduced. An increase in temperature of the lower ring at thermal processing is thereby suppressed to prevent discoloration of the gas ring.

Abstract: The present invention provides a microstructure in which evenly distributed crystal grains line up in parallel lines extending along the surface of the film, and a no-lateral-growth region left at each of locations exposed to both ends of a grain interface, which serves as a partition between the neighboring two crystal grains. According to the present invention, there are also provided: a method for forming a polycrystalline film, such as a thin polycrystalline silicon film, a thin aluminum film, and a thin copper film, which is flat and even, in surface, electrically uniform and stable, and mechanically stable; a laser crystallization device for use in manufacture of polycrystalline films, and a semiconductor device using the polycrystalline film and having good electrical property and increased breakdown voltage.

Abstract: Provided are a method of manufacturing a semiconductor device using a thermally decomposable layer, a semiconductor manufacturing apparatus, and the semiconductor device. The method includes forming an etch target layer on a substrate, forming thermally decomposable patterns spaced apart from each other on the etch target layer, forming a first mask pattern covering at least sidewalls of the thermally decomposable patterns, and removing the thermally decomposable patterns by a heating method to expose a sidewall of the first mask pattern.

Abstract: A process of preparing a wafer having a diameter of two inches or more, at least a surface of the wafer being formed from a group III nitride crystal, including preparing an alkaline or acidic etching liquid containing a peroxodisulfate ion as an oxidizing agent that accepts an electron, accommodating the wafer such that the surface of the wafer is immersed in the etching liquid such that the surface of the wafer is parallel with a surface of the etching liquid; and radiating light from the surface side of the etching liquid onto the surface of the wafer without agitating the etching liquid. First and second etching areas disposed at an interval from each other are defined on the surface of the wafer. In the process of radiating the light onto the surface of the wafer, the light is radiated perpendicularly onto surfaces of the first and second etching areas.

Abstract: A placing table configured to place a substrate on an electrostatic chuck includes a base; the electrostatic chuck placed on a placing surface of the base; and a path formed within the placing table along the placing surface, and configured to allow a heat exchange medium to flow therein from an inlet opening to an outlet opening of the heat exchange medium. A distance between a top surface of the path and the placing surface is constant from the inlet opening to the outlet opening. A cross sectional shape of the path in a direction perpendicular to the top surface is differed depending on a position in the path.

Abstract: The present technology relates to a solid-state imaging unit that makes it possible to increase the number of terminals, a method of producing the same, and an electronic apparatus. A solid-state imaging unit includes: an image sensor substrate including a light receiving region in which pixels that each convert incoming light to an electric signal are arranged in a matrix; a solder ball; a glass substrate opposite the image sensor substrate and the solder ball; and a through electrode that couples a wiring line pattern and the solder ball to each other by penetrating a glass adhesive resin interposed between the wiring line pattern and the solder ball. The solder ball is disposed outside the image sensor substrate in a plane direction. The wiring line pattern being formed on the glass substrate. The present disclosure is applicable, for example, to a package and the like including the image sensor substrate.

Abstract: A thin layer etching apparatus includes an etchant supply unit configured to supply an etchant onto a substrate to etch a thin layer formed on the substrate, a temperature measuring unit configured to measure a temperature of the substrate while an etching process is performed by the etchant, a laser irradiating unit configured to irradiate a first laser beam on a first portion including a central portion of the substrate and to irradiate a second laser beam in a ring shape on a second portion surrounding the first portion so that the temperature of the substrate is maintained at a predetermined temperature during the etching process, and a process control unit configured to control power of the first and second laser beams based on the temperature of the substrate measured by the temperature measuring unit to reduce a temperature difference between the first and second portions of the substrate.

Abstract: A substrate processing system configured to process a substrate includes a modification layer forming apparatus configured to form a modification layer within the substrate along a boundary between a peripheral portion of the substrate to be removed and a central portion of the substrate; and a periphery removing apparatus configured to remove the peripheral portion starting from the modification layer.

Abstract: Methods and apparatus for processing a substrate are provided herein.

Abstract: Gated MIS tunnel diode devices having a controllable negative transconductance behavior are provided. In some embodiments, a device includes a substrate, a tunnel diode dielectric layer on a surface of the substrate, and a gate dielectric layer on the surface of the substrate and adjacent to the tunnel diode dielectric layer. A tunnel diode electrode is disposed on the tunnel diode dielectric layer, and a gate electrode is disposed on the gate dielectric layer. A substrate electrode is disposed on the surface of the substrate, and the tunnel diode electrode is positioned between the gate electrode and the substrate electrode.

Abstract: Surface inspection apparatus includes stage for holding substrate, light source, scanning optical system for scanning light from the light source along first direction for plural times, stage scanning mechanism for scanning the stage in second direction intersecting with the first direction, and detector for detect scattered light from the substrate Inspection target region of the substrate is scanned by the light from the light source by an operation of the scanning optical system and the stage scanning mechanism. Chromatic aberration of the scanning optical system is corrected to fall within predetermined wavelength range. Fluctuation range of wavelength of the light from the light source is determined based on variation in total lighting time of the light source in scanning period of each light scanning operation along the first direction. The fluctuation range falls within the predetermined wavelength range.

Abstract: The present disclosure provides an OLED display substrate, a method for preparing the same, and a display device. The OLED display substrate includes an OLED device located on a base substrate and a packaging unit covering the OLED device. The packaging unit includes an inorganic material layer, an organic material layer, and a fluorine-doped diamond-like carbon layer located between the inorganic material layer and the organic material layer.

Abstract: A method of contaminant detection comprises exposing a wafer comprising one or more contaminants to microdroplets of an oxidizer to form an oxide on a surface of the wafer, exposing the oxide to an etchant to remove the oxide and leave the one or more contaminants on the surface of the wafer, and determining a composition of the one or more contaminants. Additional methods and related tools are also disclosed.