Abstract: A method of contaminant detection comprises exposing a wafer comprising one or more contaminants to microdroplets of an oxidizer to form an oxide on a surface of the wafer, exposing the oxide to an etchant to remove the oxide and leave the one or more contaminants on the surface of the wafer, and determining a composition of the one or more contaminants. Additional methods and related tools are also disclosed.

Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a fan-out redistribution layer (RDL) structure that has plural stacked polymer layers, plural metallization layers, plural conductive vias interconnecting adjacent metallization layers of the metallization layers, and plural rivets configured to resist delamination of one or more of the polymer layers. Each of the plural rivets includes a first head, a second head and a shank connected between the first head and the second head. The first head is part of one of the metallization layers. The shank includes at least one of the conductive vias and at least one part of another of the metallization layers.

Abstract: Provided is a method for manufacturing at least one solar cell, a method for manufacturing a monocrystalline silicon wafer and a photovoltaic module. The method for manufacturing a monocrystalline silicon wafer includes: providing a monocrystalline silicon rod; squaring the monocrystalline silicon rod to form a quasi-square silicon rod with quasi-square cross-section having an arc, a length of the arc being not less than 15 mm; slicing the quasi-square silicon rod to form at least one quasi-square silicon wafer having the arc. The method for manufacturing at least one solar cell includes: using the method described above to obtain a quasi-square silicon wafer having an arc; forming a first solar cell by processing the quasi-square silicon wafer; scribing the first solar cell to obtain a square-shaped sub-solar cell and at least one strip-shaped sub-solar cell. The above methods improve the utilization rate of the monocrystalline silicon rod and reduce production cost.

Abstract: Methods for manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate a substrate and channel layers vertically stacked over the substrate. The semiconductor structure also includes a dielectric fin structure formed adjacent to the channel layers and a gate structure abutting the channel layers and the dielectric fin structure. The semiconductor structure also includes a source/drain structure attached to the channel layers and a contact formed over the source/drain structure. The semiconductor structure also includes a Si layer covering a portion of a top surface of the source/drain structure. In addition, the Si layer is sandwiched between the dielectric fin structure and the contact.

Abstract: A 3D semiconductor device, the device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each transistor of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the transistors of the plurality of transistors, and where the second level is overlaid by a first isolation layer; and a connective path between the plurality of transistors and the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where at least one of the transistors includes a four sided gate.

Abstract: In an embodiment, a semiconductor processing tool for implementing hybrid laser and plasma dicing of a substrate is provided. The semiconductor processing tool comprises a transfer module, where the transfer module comprises a track robot for handling the substrate, and a loadlock attached to the transfer module. In an embodiment, the loadlock comprises a linear transfer system for handling the substrate. In an embodiment, the processing tool further comprises a processing chamber attached to the loadlock, wherein the linear transfer system of the loadlock is configured to insert and remove the substrate from the processing chamber.

Abstract: A method includes forming a trench within a dielectric layer, the trench comprising an interconnect portion and a via portion, the via portion exposing an underlying conductive feature. The method further includes depositing a seed layer within the trench, depositing a carbon layer on the seed layer, performing a carbon dissolution process to cause a graphene layer to form between the seed layer and the underlying conductive feature, and filling a remainder of the trench with a conductive material.

Abstract: A wafer is processed by irradiating a region to be divided with a pulse laser beam with a wavelength having absorbability to generate a thermal stress wave and propagate the wave to the inside of the region to be divided. A crushed layer is formed by executing irradiation, with a pulse laser beam with a wavelength having transmissibility with respect to the wafer, matching with a time when the thermal stress wave is generated and reaching a depth position at which a point of origin of dividing is to be generated at a sonic speed according to the material of the wafer. Absorption of the pulse laser beam with the wavelength having the transmissibility in a region in which the band gap is narrowed due to a tensile stress of the thermal stress wave forms a crushed layer that serves as the point of origin of dividing.

Abstract: A camera module and a molded circuit board assembly thereof, a semi-finished product of the molded circuit board assembly, and an array camera module and a molded circuit board assembly thereof, as well as a manufacturing method and an electronic device, wherein the camera module comprises at least one optical lens, at least one back surface molded portion, at least one photosensitive element and a circuit board.

Abstract: A system and method for performing in-situ measurements of semiconductor devices during chemical vapor deposition (CVD) includes disposing a chip carrier within a sealed chamber of a reactor for carrying out in-situ monitoring of partially fabricated semiconductor devices. The chip carrier includes a plurality of metallized bonding pads disposed along both peripheral edges on a same surface of the base for making electrical connections to metallized pads or contacts on the semiconductor device through bonding wires. Each of the plurality of metallized bonding pads disposed along both peripheral edges is electrically connected to each other as a pair through electrically connecting to a corresponding pair of ports which are disposed along both peripheral edges of the chip carrier. In-situ monitoring of the partially fabricated semiconductor device is performed through connecting the plurality of ports on the chip carrier to an external source-measure unit through a connector and wire harness.

Abstract: A laser light source is provided including an airtight container. A first resonance mirror and a second resonance mirror are disposed outside the airtight container. The first resonance mirror includes a lens unit and a reflection coating layer. The lens unit includes a first surface and a second surface, and the first surface is inclined with respect to the second surface.

Abstract: A high-quality crystalline film having less impurity of Si and the like and useful in semiconductor devices is provided. A crystalline film containing a crystalline metallic oxide including gallium as a main component, wherein the crystalline film includes a Si in a content of 2×1015 cm?3 or less.

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs).

Abstract: A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the integrated circuits include at least one processor, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

Abstract: A 3D semiconductor device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each transistor of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the transistors of the plurality of transistors, and where the second level is overlaid by a first isolation layer; and a connective path between the plurality of transistors and the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where the via includes contact with at least one of the plurality of transistors.

Abstract: A gated truncated readout system for position sensitive or imaging detectors that improves resolution over traditional readout systems. The readout system includes two or more amplifiers that receive a multichannel output analog data from the detector. Analog gates control circuitry, included in the readout circuit, receives the signals from the amplifiers, determines a fractional value of the sum-integral of the signals, and enables analog gates operation around an area of interest, disabling all other channels where noise dominates the signal value and thereby improving interpolation accuracy of the signals centroid position and the detector resolution. Filtered signals are transmitted to a centroid interpolation signal processing device for computation of the centroid position. As a result disabling all channels where noise dominates the signal value, the gated truncated readout system provides better accuracy improved detector resolution.

Abstract: A reflowable grid array (RGA) interposer includes first connection pads on a first surface of a body and second connection pads on a second surface of the body. Heating elements within the body are adjacent to the second connection pads. First interconnects within the body connect some of the second connection pads to the first connection pads. Second interconnects within the body connect pairs of the second connection pads. A motherboard assembly includes first and second components (e.g., CPU with co-processor and/or memory) and the RGA interposer. The first connection pads are in contact with motherboard contacts. The second connection pads are in contact with the first and second components. The first component passes signals directly to the motherboard by the first interconnects. The second component passes signals directly to the first component by the second interconnects but does not pass signals directly to the motherboard by the first interconnects.

Abstract: Provided is a semiconductor structure including an interconnect structure, disposed over a substrate; a pad structure, disposed over and electrically connected to the interconnect structure, wherein the pad structure comprises a metal pad and a dielectric cap on the metal pad, and the pad structure has a probe mark recessed from a top surface of the dielectric cap into a top surface of the metal pad; a protective layer, conformally covering the top surface of the dielectric cap and the probe mark; and a bonding structure, disposed over the protective layer, wherein the bonding structure comprises: a bonding dielectric layer at least comprising a first bonding dielectric material and a second bonding dielectric material on the first bonding dielectric material; and a first bonding metal layer disposed in the bonding dielectric layer and penetrating through the protective layer and the dielectric cap to contact the metal pad.

Abstract: A method for fabricating a semiconductor device includes: forming a gate structure including a source side and a drain side over a substrate, wherein a dielectric material and a columnar crystal grain material are stacked over the substrate; doping a chemical species on the drain side of the gate structure; and exposing the gate structure doped with the chemical species to a re-growth process in order to thicken the dielectric material on the drain side of the gate structure.

Abstract: An apparatus is provided which includes: a first stack including a lower, a middle, and an upper layer of conductive material with insulator layers therebetween, and a second stack including the middle and upper layers with one of the insulator layers therebetween. In an example, a first of the insulator layers has a lower breakdown voltage than a second of the insulator layers. The apparatus further includes a first via over the first stack, wherein the first via is in contact with a pair of the lower, middle and upper layers that have the first of the insulator layers therebetween. The apparatus further includes a second via over the second stack, wherein the second via extends through the upper layer and is in contact with the middle layer. In an example, the second via is isolated from a sidewall of the upper layer by a spacer.