Patents Examined by John Ruggles
  • Patent number: 7189495
    Abstract: A method of forming a photoresist layer free from a side-lobe. A mask consists of a side-lobe region, a pattern region, and an intermediate region, wherein the side-lobe region is the corresponding area of the side-lobe that used to be produced in the photoresist layer, the pattern region is the corresponding area of the pattern formed in the photoresist layer, and the intermediate region is the area between the side-lobe region and the pattern region. The method is characterized in that the transmittance of the side-lobe region is set lower than that of the intermediate region so that the side-lobe region has the light intensity lower than threshold required to trigger the photoreaction of the material for said photoresist layer.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: March 13, 2007
    Assignee: Macronix International Co., Ltd.
    Inventor: Wei-Hwa Sheu
  • Patent number: 7179570
    Abstract: A chromeless phase shift lithography (CPL) mask is described herein. The CPL mask includes a reticle having a phase-shifting feature pattern to produce a projected aerial image for patterning one or more large resist areas on a semiconductor substrate. The phase-shifting feature pattern includes an inner pattern comprising a plurality of phase-shifting features interspersed with non-phase-shifting areas. The phase-shifting features and the non-phase-shifting areas are arranged in a substantially alternating two-dimensional pattern surrounded by a substantially-filled phase-shifting peripheral area having a perimeter forming a pattern outline that is similar to an outline of the one or more large resist areas. Light that passes through the phase-shifting features and the phase-shifting peripheral area is phase-shifted by approximately 180 degrees from light passing through the non-phase-shifting areas of the CPL mask.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: February 20, 2007
    Assignee: Intel Corporation
    Inventors: Sam Sivakumar, Paul Nyhus
  • Patent number: 7160671
    Abstract: A method for increasing etching selectivity of a developed silicon-containing photoresist layer on a non-silicon containing photoresist layer on a substrate. The developed silicon-containing photoresist layer includes polymer chains containing silicon. Next, the developed silicon-containing photoresist layer and uncovered portions of the non-silicon containing photoresist layer are exposed to an ultraviolet (UV) light, where the UV light emanates from a UV generating agent, such as neon, xenon, helium, hydrogen, or krypton gas in an inert gas (e.g., argon, etc.) plasma. A top portion of the developed silicon-containing photoresist layer is then converted to a hardened layer, where the hardened layer is created by cross-linking the polymer chains containing silicon and the cross-linking is activated by the UV light. Next, an etch is performed on the uncovered portions of the non-silicon containing photoresist layer and the substrate using the hardened layer.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: January 9, 2007
    Assignee: Lam Research Corporation
    Inventors: Francis Ko, Richard Chen, Charlie Lee
  • Patent number: 7144685
    Abstract: A method of forming a latent image pattern in a photoresist film by providing a photomask for near-field light exposure that includes a transparent support and a shading member having a pattern of at least two apertures with different widths not greater than the wavelength of light from a light source. The shading member has a constant thickness that is set such that differences between light intensities directly below each of the apertures of different widths are 20% or less based on a largest light intensity of the light intensities directly below each of the apertures. The method includes placing the photomask on the photoresist film and irradiating with light from the light source. For manufacturing a semiconductor device, the method further includes developing a photoresist pattern from the latent image in the photoresist film on a silicon substrate and transferring the photoresist pattern onto the silicon substrate by etching.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: December 5, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Natsuhiko Mizutani, Yasuhisa Inao
  • Patent number: 7144682
    Abstract: A method for exposing a workpiece on the basis of near-field light escaping from an exposure mask having a light blocking film with a plurality of rectangular openings. The method includes protecting non-polarized near-field exposure light from a light source through the openings of the exposure mask to perform exposure of a pattern on the workpiece. The widths of the rectangular openings are smaller than that at a cross-point between a first curve on a coordinate of widths of the openings versus a near-field light intensity for an incident-light electric-field direction perpendicular to a lengthwise direction of a small-opening pattern and a second curve on the same coordinate for an incident-light electric-field direction parallel to the lengthwise direction of the small-opening pattern.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: December 5, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuhisa Inao, Ryo Kuroda, Natsuhiko Mizutani
  • Patent number: 7084950
    Abstract: A chromeless photomask includes a main pattern portion and a complementary pattern portion formed in the surface of the transparent mask substrate adjacent to an outer peripheral edge of the main pattern portion. The main and complementary pattern portions are each formed by recessing a surface of a transparent mask substrate to produce respective protrusions and recesses that induce a phase difference of 180 degrees in light rays passing therethrough. The complementary pattern portion is designed to produce interference that prevents distortion in the photoresist pattern formed at a region by and corresponding to the edge of the main pattern portion of the photomask. Accordingly, the present invention provides for a relatively large secondary mask alignment margin.
    Type: Grant
    Filed: April 7, 2003
    Date of Patent: August 1, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Hoon Chung, Jin-Hyung Park
  • Patent number: 7078134
    Abstract: A photolithographic mask for patterning a photosensitive material, in particular on a wafer, has at least one structure region for imaging a structure on the photosensitive material, and an absorber structure for absorbing incident radiation. At least one structure region is provided and has at least one thin protective coating of only a few atomic layers made of chemically and mechanically resistive material selected from Al2O3, Ta2O5, ZrO2, and HfO2formed by atomic layer chemical vapor deposition (ALCVD) so that the protective coating constitutes a negligible alteration of nominal or critical dimensions for the structure region, and in which additional absorption or reflection losses are negligibly low. In this way, the photolithographic mask can be cleaned chemically and/or mechanically, without the structure regions being attacked and damaged by the chemical and/or mechanical cleaning media. Furthermore, a plurality of methods are possible for fabricating this photolithographic mask.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: July 18, 2006
    Assignee: INfineon Technologies AG
    Inventors: Stefan Wurm, Siegfried Schwarzl
  • Patent number: 7067234
    Abstract: Structured resists are consolidated, that is post-exposure amplified. The amplifying agent used is a compound which contains at least one bicyclic or polycyclic group. The amplifying agent is attached via a reactive group to a reactive anchor group of a polymer that is used for the resist. The process is particularly suitable for amplifying copolymers of cycloolefins and maleic anhydride.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: June 27, 2006
    Assignee: Infineon Technologies AG
    Inventor: Jörg Rottstegge
  • Patent number: 7056624
    Abstract: Methods of manufacturing a single sided engraving phase shift mask that includes a shifter part and a non-shifter part mutually adjacent on a substrate, and a shading layer pattern formed with a shading film and wherein a side wall part of a dug-down part has round, crooked portions at top and bottom corners of the sidewall part. The method includes forming a resist pattern having a selective opening at the shifter part, forming a dug-down part corresponding to the shifter part by using the resist pattern, wet etching the whole surface at the dug-down part forming side of the substrate, forming a shading film on the substrate, forming a resist pattern on the shading film, and forming a shading pattern having prescribed openings at the shifter part and non-shifter part.
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: June 6, 2006
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventor: Haruo Kokubo
  • Patent number: 7056645
    Abstract: Method for using chromeless phase shift lithography (CPL) masks to pattern large line/space geometries. The method comprises using light at a wavelength of one of 248 nm, 193 nm, or 157 nm to illumimate a CPL mask comprising a reticle having a plurality of phase-shifting features interspersed with non-phase-shifting areas arranged in a substantially alternating two-dimensional pattern. When light passes through the phase-shifting features it is phase-shifted relative to light passing through the non-phase-shifting areas of the CPL mask. The phase-shifted light and non-phase-shifted light passing through the reticle are then projected onto a resist layer applied over a semiconductor substrate. The resultant composite aerial image intensity distribution is such that an area of the resist having a shape defined by a periphery of a corresponding pattern of phase-shifting features is sufficiently exposed to pattern a large area feature in the resist.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: June 6, 2006
    Assignee: Intel Corporation
    Inventors: Sam Sivakumar, Paul Nyhus
  • Patent number: 7052823
    Abstract: A method of manufacturing an electroconductive film subject to edge curl due to volume contraction after baking includes sequentially repeating a film-forming step of forming a film containing a photosensitive material and an electroconductive material therein and an exposure step of irradiating a light onto a desired region of the film for a plurality of times to laminate the films. The latent images of the respective layers are integrated. The resulting latent image is developed by removing a non-latent image region of the laminate film after the laminate film is formed. Finally, the developed image is baked. The sequential repetition of the film-forming step and the exposure step act to counteract edge curl formed by volume contraction after baking.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: May 30, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshimi Uda, Kazuya Ishiwata, Shinsaku Kubo, Yasuyuki Watanabe
  • Patent number: 7052809
    Abstract: A gas porous media which comprises a material having a low coefficient of thermal expansion that is capable of retaining 99.99% or more of particles of a size of about 0.003 microns and larger at 0.2 slpm/cm2 while demonstrating a permeability of 3.5×10?12 m2 and a porosity of around 62% is disclosed. The porous media can be fabricated into a frame that is capable of retaining 99.9999999% of particles greater than 0.003 ?m in diameter at 8.3 sccm/cm2 with a permeability of 3.0×10?13 m2 and a porosity of around 53%. The porous medias can be tailored by changing the raw materials and process to yield media with a range of porosities and that exhibit permeability between 1.0E?13 and 1.0E?11 m2. The porous media are used in frames for supporting a pellicle and a reticle in a parallel relationship to each other. The frames may comprise porous media in its entirety or the porous media can be fabricated and sealed into a solid support frame.
    Type: Grant
    Filed: October 2, 2003
    Date of Patent: May 30, 2006
    Assignee: Mykrolis Corporation
    Inventors: Christopher J. Vroman, Nathan Abbott
  • Patent number: 7050144
    Abstract: A photomask for near-field light exposure includes a transparent substrate, and a shading member on the substrate, a mask pattern including at least two apertures with different widths not greater than the wavelength of light from a light source. The shading member has a constant thickness that is set such that differences between light intensities directly below each of the apertures of different widths is 20% or less based on a largest light intensity of the light intensities directly below each of the apertures of different widths. A near-field light exposure apparatus includes a stage that holds the photomask, a light source, a sample table that holds a work substrate provided with a photoresist having a thickness that is less than the wavelength of exposure light, and a means for controlling the distance between the work substrate and the photomask.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: May 23, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Natsuhiko Mizutani, Yasuhisa Inao
  • Patent number: 7045274
    Abstract: A process amplifies structured resists by utilizing a reaction between a nucleophilic group and an isocyanate group or thiocyanate group to link an amplification agent to a polymer present in the photoresist. The amplification agent includes aromatic and/or cycloaliphatic groups. An isocyanate group or a thiocyanate group and a nucleophilic group form a reaction pair; one of the partners is provided on the polymer and the other partner on the amplification agent. The amplification reaction takes place more rapidly than a linkage to carboxylic anhydride groups. Furthermore, the amplification reaction permits the use of polymers which have high transparency at short wavelengths of less than 200 nm, in particular 157 nm.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: May 16, 2006
    Assignee: Infineon Technologies AG
    Inventor: Jörg Rottstegge
  • Patent number: 7045273
    Abstract: A process for the amplification of structured resists utilizes a reaction between a nucleophilic group and an isocyanate group or thiocyanate group to link an amplification agent to a polymer present in the photoresist. The isocyanate group or the thiocyanate group in addition to the nucleophilic group form a reaction pair. One of the partners is provided on the polymer and the other partner on the amplification agent. The amplification reaction takes place more rapidly than a linkage to carboxylic anhydride groups. Furthermore, the amplification reaction permits the use of polymers that have high transparency at short wavelengths of less than 200 nm, in particular 157 nm.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: May 16, 2006
    Assignee: Infineon Technologies AG
    Inventors: Jens Ferbitz, Werner Mormann, Jens Rottstegge, Christoph Hohle, Christian Eschbaumer, Michael Sebald
  • Patent number: 7033708
    Abstract: A focus monitor on an alternating phase shift mask may include sub-wavelength features which have a depth corresponding to an etch depth of primary features on the mask (e.g., a 180° etch depth), but which produce an effective phase shift of about 60° to 120°.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: April 25, 2006
    Assignee: Intel Corporation
    Inventor: Edita Tejnil
  • Patent number: 7026078
    Abstract: First, a correction is made for correcting the mask pattern configuration of a photomask (3) used for exposure in accordance with the space between a mask pattern and an adjacent mask pattern thereto and a desired configuration to be transferred from the mask pattern. Second, a correction is made for dividing the photomask (3) into a plurality of mesh regions (M) to correct the pattern configuration of the photomask (3) in accordance with the occupation rate (R) of the mask pattern in each of the mesh regions (M).
    Type: Grant
    Filed: August 7, 2003
    Date of Patent: April 11, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Kawashima, Yoshitaka Yamada
  • Patent number: 7018753
    Abstract: A method of fabricating integrated circuits according to a first design by imaging a first layer on a substrate using a first mask having a block of first patterns in common with a second design, but without any other patterns of the first or second designs and imaging a second layer on the substrate using a second mask having a block of second patterns unique to the first design and at least one third layer pattern. The block of first patterns is repeatedly exposed in a first grid and the block of second patterns is repeatedly exposed in a second grid, each without overlap in the corresponding layer. The grids are aligned such that the integrated circuits and test structures in scribe lines between the integrated circuits are properly formed on the substrate. The first patterns can be for large fields and the second patterns can be for small fields.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: March 28, 2006
    Assignee: LSI Logic Corporation
    Inventors: David J. Sturtevant, Duane B. Barber, Ann I. Kang
  • Patent number: 7014961
    Abstract: A photomask assembly is described having a frame for supporting a transparent pellicle above a photomask substrate, defining a closed pellicle space overlaying the substrate. The frame is formed of a porous material configured to allow the pellicle space to be purged with an inert gas within a reasonable processing time period, thereby removing any harmful chemicals that might be present. The frame preferably is made by a method that includes preparing a gel by a sol-gel process, drying the gel, and partially densifying the dry gel. The resulting frame has a gas permeability to oxygen or nitrogen higher than about 10 ml.mm/cm2.min.MPa, an average pore size between 0.001 micrometer and 10 micrometers, and a coefficient of thermal expansion between 0.01 ppm/° C. and 10 ppm/° C.
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: March 21, 2006
    Assignee: Yazaki Corporation
    Inventors: Rahul Ganguli, Troy Robinson, D. Laurence Meixner
  • Patent number: 7016387
    Abstract: A semiconductor laser element that has window regions at its opposite end faces and an electrode portion superposed on an inner portion of the upper surface thereof to include covering an inner portion of the upper surfaces of the window regions without covering the entire upper surfaces of the window regions, by aligning a photomask for forming electrode pattern segments at a predetermined position over a laser substrate, which includes a plurality of element regions in a matrix pattern and a plurality of window region pattern stripes corresponding to the window regions of the element regions, the electrode pattern segments being used for forming electrodes at predetermined positions between the adjacent window region pattern stripes, wherein the photomask includes: an electrode pattern region for forming the electrode pattern segments; and an auxiliary mask having a scale section for measuring the amount of alignment deviation of the electrode pattern segments with respect to the window region pattern.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: March 21, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Masayuki Ohta