Abstract: A method for repairing a defective photomask having contained therein a minimum of one defect within a defective pattern employs a non-defective photomask for purposes of photoexposing a photoresist layer formed upon the defective photomask such as to form a patterned photoresist layer which leaves exposed the minimum of one defect. The minimum of one defect may then be repaired with the patterned photoresist layer in place as a repair mask. The method also provides for use of a non-defective pattern region within a defective photomask in a like fashion for repairing a defective pattern region within the same photomask. The method may be extended to repairing defective microelectronic products.
Abstract: A process for producing amplified negative resist structures that includes exposing and contrasting of a resist then simultaneously developing and amplifying the resist to form the amplified resist structures. This substantially simplifies the production of amplified resist structures. Amplifying agents used include bicyclic or polycyclic compounds containing at least one reactive group for attachment to the resist polymer.
Abstract: A set of masks including an alternating phase shifting mask (APSM) and a halftone phase shifting trim mask (HPSTM) is provided. The APSM includes first and second phase shifting areas and a first opaque pattern. The first and second phase shifting areas are disposed adjacent to each other and have different phases for generating destructive interference. Further, the first and second phase shifting areas define an access interconnection line. The first opaque pattern is formed on a transparent substrate to define the first and second phase shifting areas. The HPSTM includes a second opaque pattern on the transparent substrate and a halftone pattern. The second opaque pattern prevents an access interconnection line from being erased. The halftone pattern defines a pass interconnection line connected to the access interconnection line.
Type:
Grant
Filed:
November 22, 2002
Date of Patent:
February 14, 2006
Assignee:
Samsung Electronics Co., Ltd.
Inventors:
Chul-Hong Park, Moon-Hyun Yoo, Yoo-Hyon Kim, Dong-Hyun Kim, Soo-Han Choi
Abstract: A dual damascene process is disclosed which reduces capacitance increases caused by excess and unnecessary remnants of an etching stop layer and which also improves multi-level interconnect structures by removing the etching stop layer except for a portion that surrounds the via hole. This reduces or eliminates capacitance increase and avoids erosion of underlying interlayer insulating layers during formation of an upper, wider trench.
Abstract: A resist pattern forming method using a coating and developing apparatus and an aligner being connected thereto which are controlled to form a resist film on a surface of a substrate with a base film and a base pattern formed thereon, followed by inspecting at least one of a plurality of measurement items selected from: reflection ratio and film thickness of the base film and the resist film, line width after a development, an accuracy that the base pattern matches with a resist pattern, a defect on the surface after the development, etc. A parameter subject to amendment is selected based on corresponding data of each measurement item, such as the film thickness of the resist and the line width after the development, and amendment of the parameter is performed. This results in a reduced workload of an operator, and an appropriate amendment can be performed.
Abstract: A method for protecting a semiconductor process wafer surface from contacting thermally degraded photoresist including providing a semiconductor process wafer having a process surface; forming a protective layer over selected areas of the process surface said protective layer including a resinous organic material having a glass transition temperature (Tg) that is about greater than a thermal treatment temperature; forming a photoresist layer over at least a portion of the protective layer to include a photolithographic patterning process; and subjecting the semiconductor process wafer to the thermal treatment temperature.
Abstract: In a method of manufacturing an electroconductive film, a developing process is implemented on a photosensitive paste layer (12) having a height of about 13 ?m in a state where exposure is repeated twice in FIG. 1D, and thereafter, a baking process is completed to form a wiring pattern (20). As a result, the curling of an edge formed in the wiring pattern (20) can be remarkably reduced.
Abstract: The invention provides a coated metal substrate comprising a metal substrate having an outer surface, a maskant film adhered to at least a portion of the outer surface of the metal substrate, the maskant film having a pattern of scribed lines therein, and a line sealant composition applied to the scribed lines in a maskant film. Both the maskant film and the line sealant composition are preferably radiation cured and substantially solvent-free. The invention also provides a method of protecting a metal substrate from chemical exposure by utilizing the radiation-cured maskant film and line sealant composition.
Abstract: The invention relates to a process for producing amplified negative resist structures in which, following exposure and contrasting of the resist, the resist structure is simultaneously developed and aromatized. This substantially simplifies the production of amplified resist structures. Amplifying agents include compounds having not only a reactive group for attachment to an anchor group of the polymer, but also at least one aromatic group.
Type:
Grant
Filed:
July 1, 2002
Date of Patent:
September 20, 2005
Assignee:
Infineon Technologies AG
Inventors:
Jörg Rottstegge, Eberhard Kühn, Christian Eschbaumer, Gertrud Falk, Michael Sebald
Abstract: The present invention provides a method, article of manufacture and system for fabricating an article using photo-activatable building material. The method includes the steps of applying a layer of the photo-activatable building material to a preselected surface, scanning the layer using a plurality of light-emitting centers to photo-activate the layer of photo-activatable building material in accordance with a predetermined photo-initiation process to obtain polymerization of the building material, wherein scanning is accomplished at a predetermined distance using a predetermined light intensity, and repeating the steps of applying the layer, with each layer being applied to an immediately previous layer, and scanning the layer with the plurality of light-emitting centers to polymerize the building material until the article is fabricated.
Type:
Grant
Filed:
October 29, 2001
Date of Patent:
August 9, 2005
Assignee:
Hewlett-Packard Development Company, L.P.
Abstract: A thin film to be milled is formed on a substrate 1, and thereafter, a polymethylglutarimide layer and a photoresist layer are coated. Then, the photoresist layer is exposed and developed via a given mask, to form a pre-resist pattern. Then, ashing treatment is performed for the pre-resist pattern to a narrowed resist pattern. Subsequently, the thin film to be milled is milled via the resist pattern to obtain a patterned thin film.
Abstract: A process for chemically amplifying structured resists includes applying a chemically amplified resist to a substrate and structuring it in a customary manner. Preferably, the amplification agent is applied in an aqueous phase to the structured resist and, after chemical amplification is complete, excess agent is removed by an aqueous wash medium. By using water as a solvent for the amplification agent and as a wash medium, it is possible to avoid organic solvents that constitute an explosion hazard. Furthermore, removal of partially exposed resist sections is suppressed.
Type:
Grant
Filed:
February 28, 2003
Date of Patent:
May 31, 2005
Assignee:
Infineon Technologies AG
Inventors:
Siew Siew Yip, Jörg Rottstegge, Ernst-Christian Richter, Gertrud Falk, Michael Sebald, Kerstin Seibold, Marion Kern