Patents Examined by John Trimmings
  • Patent number: 9026887
    Abstract: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: May 5, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Troy A. Manning, Troy D. Larsen, Martin L. Culley
  • Patent number: 8972811
    Abstract: A panel driving circuit that produces a panel test pattern and a method of testing a panel are provided. The driving circuit includes a pattern generation unit and a selection unit. The pattern generation unit responds to a system clock and produces pattern test data and pattern test signals. The selection unit responds to a test signal and selects and outputs either (a) the pattern test data and the pattern test signals that are outputted from the pattern generation unit, or (b) the pattern test data and pattern test signals that are directly applied from the outside. The driving circuit and the method of the panel test generates the panel test data, the horizontal synchronizing signal, the vertical synchronizing signal, and the data activating signal within the driving circuit using a system clock so that the testing of the panel can be carried out without using a separate test device.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Sik Kang, Jae-Goo Lee
  • Patent number: 8965939
    Abstract: A method begins, in accordance with a segmentation approach, dividing large data to be stored into regions and dividing a region into segments. The method continues by generating preliminary DSN storage information for one or more regions. The method continues by identifying other large data stored in the DSN that has a relationship with the large data to be stored in the DSN and retrieving DSN storage information for the other large data. The method continues by comparing, at a region level, the preliminary DSN storage information with the retrieved DSN storage information. When a region of the large data to be stored has substantially similar DSN storage information as a region of the other large data, the method continues by utilizing the DSN storage information for the region of the other large data for the DSN storage information of the region of the large data.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: February 24, 2015
    Assignee: Cleversafe, Inc.
    Inventors: Wesley Leggette, Jason K. Resch
  • Patent number: 8966354
    Abstract: A communication system having a main control portion (MCP) to transmit information destined to a device n cascade levels down, and create an error detection code (CRC code) for data that contains a count of remaining cascade levels until an n-th cascade level and the information. The code is transmitted to an upstream sub-control portion (USCP) with the data. The USCP creates a CRC code for the data, and compares the created and received codes. For a match, the USCP determines whether the information is destined to itself based on the remaining cascade level count. When the information is not so destined, the USCP creates new data with the remaining cascade level count reduced by 1, and a CRC code for the new data, and transmits the created code to a further device, with the new data.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: February 24, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Daisuke Morikawa
  • Patent number: 8959411
    Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Kanno, Hironori Uchikawa
  • Patent number: 8954820
    Abstract: A custom decoding algorithm is introduced, in connection with a corresponding decoding structure, to resolve many complexity and large memory requirements of known decoders. A system. A variable node forms a confidence vector of four components, one component for each state of a memory cell, and passes the current primary component (e.g., the largest) to one or more check nodes. The check nodes calculate a temporary component and corresponding index based on all components received from the variable nodes, which they pass back to the respective variable nodes. The variable node updates the confidence vector based on the temporary nodes received from respective check nodes, and determines the correct state for corresponding memory cell based on which component in the confidence vector is currently the primary component.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: February 10, 2015
    Assignee: STEC, Inc.
    Inventors: Majid Nemati Anaraki, Xinde Hu, Richard D. Barndt
  • Patent number: 8943386
    Abstract: Bin identification information for a cell is generated. An estimation function is received where the estimation function trends toward a maximum soft read value at a first end and trends toward a minimum soft read value at a second end. A soft read value is determined for the cell based at least in part on the bin identification information and the estimation function.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: January 27, 2015
    Assignee: SK hynix memory solutions inc.
    Inventors: Frederick K. H. Lee, Jason Bellorado, Marcus Marrow
  • Patent number: 8938659
    Abstract: Described embodiments provide a media controller that performs error correction on data read from a solid-state media. The media controller receives a read operation from a host device to read one or more given read units of the solid-state media. The media controller reads the data for the corresponding read units from the solid-state media employing initial values for one or more read threshold voltages. Only if a disparity between an actual number of bits at a given logic level included in the read data and an expected number of bits at the given logic level included in the read data has not reached a predetermined threshold, the media controller decodes the read data and provides the decoded data to the host device.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: January 20, 2015
    Inventors: YingQuan Wu, Earl T. Cohen
  • Patent number: 8935582
    Abstract: Embodiments of the disclosed technology comprise software-based techniques that can be used to improve scan chain test pattern generation and scan chain failure diagnosis resolution. For example, certain embodiments can be used to generate high quality chain diagnosis test patterns that are able to isolate a scan chain defect to a single scan cell. Such embodiments can be used to generate a “complete” test set—that is, a set of chain diagnosis test patterns that is able to isolate any scan chain defect in a faulty scan chain to a single scan cell.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: January 13, 2015
    Assignee: Mentor Graphics Corporation
    Inventors: Ruifeng Guo, Yu Huang, Wu-Tung Cheng
  • Patent number: 8930798
    Abstract: Methods and apparatus are provided for encoding input data for recording in s-level storage of a solid state storage device, where s f 2. Input data words are encoded in groups of M input data words in accordance with first and second BCH codes to produce, for each group, a set of M first codewords of the first BCH code. The set of M first codewords is produced such that at least one predetermined linear combination of the M first codewords produces a second codeword of the second BCH code, this second BCH code being a sub-code of the first BCH code. The sets of M first codewords are then recorded in the s-level storage. If each of the first and second codewords comprises N q-ary symbols where q=pk, k is a positive integer and p is a prime number, the q-ary code alphabet can be matched to the s-ary storage by ensuring that q and s are uth and vth powers respectively of a common base r, where u and v are positive integers and k f u, whereby p(k/u)v=s.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Roy D. Cideciyan, Evangelos S. Eleftheriou, Thomas Mittelholzer
  • Patent number: 8924826
    Abstract: A method for encoding data words into a frame is provided. Input data words are received on a first bus having a first width. The input data words are buffered so as to output intermediate data words onto a second bus having a second width. A transcode bit is generated from the intermediate data words, and a set of parity bits is generated from the intermediate words using a syndrome generator, where the syndrome generator uses a number of bits that are equal to the second width. A frame is then generated from the intermediate data words and the set of parity bits and is output to a third bus having the first width.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: December 30, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Seuk B. Kim, Douglas E. Wente
  • Patent number: 8924801
    Abstract: An integrated circuit comprises scan test circuitry and at least one circuit core coupled to the scan test circuitry. The scan test circuitry comprises input and output scan chains coupled to respective input and output interfaces of the circuit core via respective functional logic blocks, and interface signal selection circuitry. The interface signal selection circuitry is configured to select a particular one of a functional input signal and a plurality of scan test input signals for application to one or more designated input signal lines of the input interface of the circuit core responsive to one or more control signals. By way of example only, the first and second scan test input signals may comprise respective first and second distinct address values and the designated input signal lines of the input interface of the circuit core may comprise address input signal lines of an embedded memory.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: December 30, 2014
    Assignee: LSI Corporation
    Inventors: Ramesh C. Tekumalla, Prakash Krishnamoorthy
  • Patent number: 8924824
    Abstract: An error management system for a data storage device can generate soft-decision log-likelihood ratios (LLRs) using multiple reads of memory locations. 0-to-1 and 1-to-0 bit flip count data provided by multiple reads of reference memory locations can be used to generate probability data that is used to generate possible LLR values for decoding target pages. Possible LLR values are stored in one or more look-up tables.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: December 30, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventor: Guangming Lu
  • Patent number: 8918705
    Abstract: One or more locations in a plurality of data bit sequences that do not satisfy parity and are associated with data bit sequences that are unable to be successfully error correction decoded are determined. Soft information associated with the determined locations is modified and error correction decoding using the modified soft information is performed.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: December 23, 2014
    Assignee: SK hynix memory solutions inc.
    Inventors: Xiangyu Tang, Yingquan Wu
  • Patent number: 8918685
    Abstract: This technology relates to smoothly performing a test on a memory circuit having a high memory capacity while reducing the size of a test circuit. A test circuit according to the present invention includes a test execution unit configured to perform a test on a target test memory circuit, an internal storage unit configured to store data for the test execution unit, and a conversion setting unit configured to set a part of or the entire storage space of the target test memory circuit as an external storage unit for storing the data for the test execution unit.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: December 23, 2014
    Assignee: SK Hynix Inc.
    Inventors: Hyung-Gyun Yang, Hyung-Dong Lee, Yong-Kee Kwon, Young-Suk Moon, Hong-Sik Kim
  • Patent number: 8904250
    Abstract: Testing methods in a pre-programmed memory device after it has been assembled into a final customer platform include issuing a self-test command to the memory device, the memory device reporting results of a self-test of pre-programmed data executed responsive to receiving the self-test command, and issuing a self-repair command responsive to the results indicating repair of the pre-programmed data is needed.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: December 2, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Francesco Falanga, Victor Tsai
  • Patent number: 8898548
    Abstract: A data storage device may comprise an array of flash memory devices and a controller coupled thereto, configured to program and read data from the array responsive to received data access commands. The array may comprise a plurality of blocks, each comprising a plurality of flash pages (F-Pages), each of which comprising an integer number of one or more error correcting code pages (E-Pages), at least some of which comprising a data portion and an error correction code (ECC) portion. The controller may be configured to store a plurality of logical pages (L-Pages) in one or more of the plurality of E-Pages, at least some being unaligned with boundaries of the E-Pages; and to adjust, in at least one of the blocks, the size of the ECC portion and correspondingly adjust the size of the data portion of the E-Pages.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: November 25, 2014
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rodney N. Mullendore, Radoslav Danilak, Justin Jones, Andrew J. Tomlin
  • Patent number: 8898549
    Abstract: A method for implementing adaptive error correction in a memory, comprising the steps of (A) decoding a page of data read from a memory, (B) selecting one of a plurality of histograms based on a measured code word error rate of the decoded page and (C) applying an error correction code rate based on the selected histogram. The error correction code rate allows the memory to use a minimum number of error correction bits to provide reliable operation of the memory.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: November 25, 2014
    Assignee: Seagate Technology LLC
    Inventors: Alexander Hubris, Hao Zhong
  • Patent number: 8898550
    Abstract: A data encoding method for encoding a sequence of N input blocks of bits into an output block for transmission includes adding an L-bit control indicator, indicating whether the sequence contains any control blocks, and if so, producing an output block in which the order of data and control blocks is preserved by deleting a set of bits from the block-type field of at least one control block, adding to the sequence an N-bit position indicator indicating positions of data and control blocks in the sequence, and providing in bit positions of remaining bits of the block-type field of the at least one control block an indication of the type of that control block; wherein the position indicator bits are added at bit-positions such that, in a header-first transmission order of the output block, all data and control blocks succeed the position indicator bits indicating positions of those blocks.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: November 25, 2014
    Assignee: International Business Machines Corporation
    Inventor: Roy D. Cideciyan
  • Patent number: 8887029
    Abstract: A communication device includes a turbo encoding section including a plurality of component encoders, wherein the plurality of component encoders within the turbo encoding section use different constraint lengths.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: November 11, 2014
    Assignees: Sharp Kabushiki Kaisha, Osaka University
    Inventors: Jungo Goto, Yasuhiro Hamaguchi, Kazunari Yokomakura, Osamu Nakamura, Hiroki Takahashi, Shinsuke Ibi, Seiichi Sampei, Shinichi Miyamoto