Abstract: A display system and a method of displaying an image are hereby presented. The display system is arranged to display an image on a screen which has at least one useful screen area which is intended to be seen by a user and at least one non-useful screen area which the user cannot see. The display device comprises a bandwidth saver unit arranged to determine a location on the screen of a current pixel to be displayed. If the pixel is located in a non-useful screen area of the screen, then the fetching from a data memory of a pixel value is inhibited by the bandwidth saver unit with respect to this pixel, and a replacement, fixed pixel value is passed to a data processing unit for further processing.

Abstract: Embodiments for providing personal broadcast are generally described herein. A computing device to display a personal bulletin board may comprise a transceiver configured to data at the computing device from a second computing device; a rear-facing screen configured to present an indication of the data to a user of the first computing device; an input module configured to receive a command from the user to display a representation of the data on the front-facing screen; and a front-facing screen configured to display the representation of the data in response to receiving the command from the user.

Abstract: In one embodiment, a method comprising grouping by a processor primitives that comprise a scene into plural clusters, each cluster comprising a subset of the primitives that are proximal to each other relative to the other of the primitives; and allocating an equal size memory block for each respective cluster for the plural clusters, wherein all the plural clusters comprise one scene representation, wherein each cluster can contain up to M primitives, where M is an integer number.

Abstract: A frame pacing method, computer program product, and computing system are provided for graphics processing. A method and system for frame pacing adds a delay which evenly spaces out the display of the subsequent frames, and a measurement mechanism which measures and adjusts the delay as application workload changes in an evenly spaced manner.

Abstract: A method of writing image data to a pixel array includes decoding an address and activating, based on the decoded address, two or more row selection signals. The address may be a ternary address having at least one trit. The method further includes providing the two or more row selection signals to the pixel array to select two or more rows of the pixel array, the activation of which writes the image data to pixels in the two or more rows of the pixel array.

Abstract: A system comprises light intensity detection circuitry and pixel data processing circuitry. The light intensity detection circuitry is operable to determine whether a welding arc is present based on an intensity of light incident captured by the light intensity detection circuitry, and generate a control signal indicating a result of the determination. A mode of operation of the image processing circuitry may be selected from a plurality of modes based on the control signal. The light intensity detection circuitry may comprise, for example, a passive infrared sensor, a photodiode, and/or circuitry of a camera. The pixel data processing circuitry may comprise, for example, circuitry of a camera, a special purpose graphics processing unit, and/or a general purpose processing unit.

Abstract: A mapping system disclosed herein includes a requestor that transmits requests for different layer sets of mapping data for a digital map to one or more data sources across a network according to a predefined order. According to one implementation, the mapping system also processes and/or renders the different layer sets to a display according to the predefined order.

Abstract: One device generates a first screen by executing some processes including a first process of rendering processing of the screen to be displayed in accordance with the information required to determine the rendered contents. On the other hand, devices except for the one device generates a second screen by executing some processes, which do not include the first process but include a second process different from the first process, of the rendering processing of the screen to be displayed in accordance with that information, and sends the second screen to the one device. Then, the one device receives the second screens generated by the respective devices except for the one device, and generates the screen to be displayed by compositing the first and second screens.

Abstract: Graphics cards normally control the image display of data processing systems.

Abstract: A portable data terminal including a multi-core processor having at least a first core and a second core, at least one illumination assembly and at least one imaging assembly and data storage means configured to store a plurality of program instructions, the program instructions including at least one one-dimensional decoder and at least one two-dimensional decoder.

Abstract: A display pipe is configured to generate output frames for display. Additionally, the display pipe may be configured to compress an output frame and write the compressed frame back to memory responsive to detecting static content in successive output frames. The display pipe may also be configured to determine to selectively allow write-back logic to operate when doing so will not cause a pixel underrun to the display. If an underrun might occur, write-back logic is temporarily disabled. If write-back is successful, the display pipe may read the compressed frame from memory for display instead of reading the source frames for compositing and display.

Abstract: A circuit diagram supplying apparatus 10, for supplying a user with whole contents of an device system circuit diagram, then requests a server 30 for first-of-all transmission of part-connection-drawing overall circuit diagram data in which connection diagrams LSd are added to a part placement diagram included in the circuit diagram and having electrical component parts PSd arranged therein. Then, after displaying a part-connection-drawing overall circuit diagram based on the transmitted and received part-connection-drawing overall circuit diagram data, the circuit diagram supplying apparatus 10 requests the server 30 for sequential transmission of circuit-element-drawing divisional circuit diagram data (a)-(e).

Abstract: A data processing apparatus has a de-compressor and an input interface. The de-compressor de-compresses a compressed display data in an input bitstream. The input interface receives the input bitstream from another data processing apparatus via a display interface, parses indication information included in the input bitstream, and configures the de-compressor to employ a de-compression algorithm according to the indication information.

Abstract: The wireless electronic retail price tag system is a display system for retail shelves. The wireless electronic retail price tag system is a wireless electronic display that attaches readily on shelves and that is used for displaying product, price, and marketing information items on the shelves. The wireless electronic retail price tag system is adapted to communicate with and to be updated by a master computer located in a secure location. The wireless electronic retail price tag system comprises an LCD, a microcontroller, a remote wireless interface, and a housing.

Abstract: Input amount calculation processing and output amount calculation processing corresponding to each processing module are defined. The input amount calculation processing and the output amount calculation processing are performed in a processing order (a reverse order to the processing order) to obtain a favorable peripheral pixel amount.

Abstract: In several embodiments, a graphics processor couples to a virtual machine monitor (VMM) to present a virtual graphics processor to one or more virtual machines. A mediator for the virtual graphics processor synchronously shadows modifications to a guest graphics translation table (GTT) of a virtual machine to a shadow GTT of the VMM using trap and emulate virtualization. If the mediator detects a frequency of modifications to the guest GTT that exceeds a threshold the mediator may then asynchronously shadow at least a portion of the guest GTT to the shadow GTT and rebuild the shadow GTT prior to submitting commands for the virtual graphics processor to the graphics processor.

Abstract: Disclosed herein are system, apparatus, article of manufacture, method, and/or computer program product embodiments for providing a representation to a connected device. An embodiment operates by recognizing a new device connected to a display device, collecting device fingerprint information from the new device, and requesting a device class representation information determined based on the device fingerprint information. Another embodiment operates by receiving device fingerprint information from a display device via a network connection, wherein the device fingerprint information is collected from a device connected to a display device, and providing device class representation information to the display device via the network connection, when the device class representation information corresponding to the device fingerprint information is available.

Abstract: A tile-based graphics processing pipeline comprising a rasteriser 3, a renderer 6, a tile buffer 10 configured to store rendered fragment data locally to the graphics processing pipeline prior to that data being written out to an external memory, a write out stage 13 configured to write data stored in the tile buffer to an external memory, and a programmable processing stage 14. The programmable processing stage 14 is operable under the control of graphics program instructions to read fragment data stored in the tile buffer 10 on a random access basis, perform a processing operation using the read fragment data, and write the result of the processing operation into the tile buffer 10 or to an external memory.

Abstract: A graphical processing unit having an implementation of a hierarchical hash table thereon, a method of establishing a hierarchical hash table in a graphics processing unit and GPU computing system are disclosed herein. In one embodiment, the graphics processing unit includes: (1) a plurality of parallel processors, wherein each of the plurality of parallel processors includes parallel processing cores, a shared memory coupled to each of the parallel processing cores, and registers, wherein each one of the registers is uniquely associated with one of the parallel processing cores and (2) a controller configured to employ at least one of the registers to establish a hierarchical hash table for a key-value pair of a thread processing on one of the parallel processing cores.

Abstract: Approaches are disclosed for performing memory access operations in a texture processing pipeline having a first portion configured to process texture memory access operations and a second portion configured to process non-texture memory access operations. A texture unit receives a memory access request. The texture unit determines whether the memory access request includes a texture memory access operation. If the memory access request includes a texture memory access operation, then the texture unit processes the memory access request via at least the first portion of the texture processing pipeline, otherwise, the texture unit processes the memory access request via at least the second portion of the texture processing pipeline. One advantage of the disclosed approach is that the same processing and cache memory may be used for both texture operations and load/store operations to various other address spaces, leading to reduced surface area and power consumption.