Abstract: In a method of operating an application processor to control a display device including a non-rectangular valid display region, screen information regarding the non-rectangular valid display region is received, and a plurality of pieces of valid pixel data selected based on the screen information and corresponding to the non-rectangular valid display region are output to the display device.

Abstract: A reception unit receives an image file from other electronic device. A display processing unit displays an image related to acquisition of content together with a content image if content identification information is included in an acquired image file. The display processing unit displays, as an image relating to acquisition of content, a link button which permits access to a content server.

Abstract: A graphics processing unit is configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles. The graphics processing unit comprises one or more processing cores configured to process graphics data. The graphics processing unit also comprises cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing the set of one or more tiles. The graphics processing unit also comprises scheduling logic configured to schedule, in dependence upon the cost indications, the sets of one or more tiles for processing on the one or more processing cores.

Abstract: Examples are disclosed herein that relate to constraining communication among HMD devices. One example provides a computing system comprising a logic machine and a storage machine holding instructions. The instructions are executable to receive, for each of a plurality of head-mounted display devices, vantage point data, determine, for each of the plurality of head-mounted display devices, whether one or more other head-mounted display devices are within a vantage point scope of that head-mounted display device, the vantage point scope being based on the vantage point data of that head-mounted display device, and constrain, for each of one or more head-mounted display devices, delivery of communication data from that head-mounted display device to one or more of the plurality of head-mounted display devices, such constraint based on whether that head-mounted display device is within the vantage point scope of one or more of the plurality of head-mounted display devices.

Abstract: A display device comprises a display panel having a plurality of pixels arranged in pixel rows and pixel columns, and a source circuit. The source circuit includes a plurality of signal lines, each signal line coupled to each pixel of a pixel column; a plurality of column drivers, each column driver connected to one of the signal lines so as to transmit pixel voltages to the pixels of its respective pixel column, the pixel voltages corresponding to image data values for displaying an image upon the display panel; and a plurality of pixel refresh circuits. Each pixel refresh circuit corresponds to one of the signal lines and is coupled to the respective column driver so as to be arranged to determine a voltage stored in the corresponding pixel and to transmit a refresh signal to the respective column driver to refresh the voltage stored in the corresponding pixel.

Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.

Abstract: A graphics processing system processes primitive fragments using a rendering space which is sub-divided into tiles. The graphics processing system comprises processing engines configured to apply texturing and/or shading to primitive fragments. The graphics processing system also comprises a cache system for storing graphics data for primitive fragments, the cache system including multiple cache subsystems. Each of the cache subsystems is coupled to a respective set of one or more processing engines. The graphics processing system also comprises a tile allocation unit which operates in one or more allocation modes to allocate tiles to processing engines. The allocation mode(s) include a spatial allocation mode in which groups of spatially adjacent tiles are allocated to the processing engines according to a spatial allocation scheme, which ensures that each of the groups of spatially adjacent tiles is allocated to a set of processing engines which are coupled to the same cache subsystem.

Abstract: A computerized method, system, and computer program product can allow for processing by a processor data records (xDRs). The method can include receiving by the processor xDRs, each xDR including a vector of unique data fields, the xDRs forming together a stream. The stream can be stored by the processor in a memory of a general purpose graphic processor unit (GPGPU). An index vector of xDRs can be created by the processor, wherein each xDR is assigned a unique index identifier, and stored by the processor in a memory of the GPGPU. The index vector of xDRs is sorted with respect to at least a key of at least a unique data element selected. The sorted index vector can be stored in the memory of the GPGPU. A selection of at least the unique data field can be performed and aggregation of the stream performed with respect to the selection.

Abstract: Processing of non-real-time and real-time workloads is performed using discrete pipelines. A first pipeline includes a first shader and one or more fixed function hardware blocks. A second pipeline includes a second shader that is configured to emulate the at least one fixed function hardware block. First and second memory elements store first state information for the first pipeline and second state information for the second pipeline, respectively. A non-real-time workload executing in the first pipeline is preempted at a primitive boundary in response to a real-time workload being dispatched for execution in the second pipeline. The first memory element retains the first state information in response to preemption of the non-real-time workload. The first pipeline is configured to resume processing the subsequent primitive on the basis of the first state information stored in the first memory element.

Abstract: An information processing device includes a first memory, a second memory, and a memory control circuit. The first memory stores first information. The second memory stores second information different from the first information. The memory control circuit controls reading and writing of the first information on the first memory and reading and writing of the second information on the second memory. The first information is read and written more frequently than the second information, and takes less time to be read than the second information.

Abstract: A vehicle display system includes: a display arranged in a cabin of a vehicle and configured to display settings of a plurality of setting items of an air conditioner; and an electronic control unit configured to calculate an index value indicating a level of an operating load of the air conditioner on the basis of the setting of the setting item that influences a load state of the air conditioner among the plurality of setting items, and display, on the display unit, the index value and the setting of the setting item used to calculate the index value among the plurality of setting items.

Abstract: A method includes providing a three-dimensional virtual environment by executing instructions and displaying the environment in two dimensions on a display screen of a computerized appliance, defining a matrix of cells within space of the virtual environment having objects with surfaces positioned by coordinates virtual environment, determining relative occupancy values for cells intersection of objects with cells, determining in the direction of light sources, relative illumination values for the cells with consideration of intensity and direction and occupancy values, including occlusion effects from cell to cell, and displaying illumination effects on surfaces of objects by managing pixel colors and intensity according to illumination values of adjacent cells.

Abstract: An image processor, an application processor, a method of operating an image processor, and a chips set of an image processor are provided. The image processor includes a scaler configured to perform scaling on an input image and generate a scaled input image; and a selection circuit configured to transmit the scaled input image to either a low latency memory or a high density memory according to a memory selection signal. The application processor includes a memory configured to store an input image; and an image processor configured to scale the input image, wherein the image processor comprises a scaler configured to perform scaling on the input image and generate a scaled input image and a selection circuit configured to transmit the scaled input image to either a low latency memory or a high density memory according to a memory selection signal.

Abstract: A system and method including, in some embodiments, receiving a request for a graphics memory address for an input/output (I/O) device assigned to a virtual machine in a system that supports virtualization, and installing, in a graphics memory translation table, a physical guest graphics memory address to host physical memory address translation.

Abstract: An embodiment of a graphics apparatus may include a frame divider to divide a frame into two or more sub-frames, and a parallelized post-render stage communicatively coupled to the frame divider to process a sub-frame of the two or more sub-frames in parallel with a render operation. The parallelized post-render stage may include a post-processor communicatively coupled to the frame divider to post-process a rendered sub-frame in parallel with the render operation. Other embodiments are disclosed and claimed.

Abstract: A method and system for a command processor for efficient processing of a program multi-processor core system with a CPU and GPU. The multi-core system includes a general purpose CPU executing commands in a CPU programming language and a graphic processing unit (GPU) executing commands in a GPU programming language. A command processor is coupled to the CPU and CPU. The command processor sequences jobs from a program for processing by the CPU or the GPU. The command processor creates commands from the jobs in a state free command format. The command processor generates a sequence of commands for execution by either the CPU or the GPU in the command format. A compiler running a meta language converts program data for the commands into a first format readable by the CPU programming language and a second format readable by the GPU programming language.

Abstract: In one example, a system for transmitting data comprises a processor to load a configuration database into memory accessible by the graphics processing unit. The processor can also detect a predetermined maximum data rate to be supported by a transmitter from the configuration database. Furthermore, the processor can transmit data from the graphics processing unit to a sink device at the predetermined maximum data rate via the transmitter and a high-definition multimedia interface link.

Abstract: One embodiment may include media circuits, an application processor, a direct memory access circuit (DMA), and a media managing circuit. The application processor may issue media commands into a queue. The media managing circuit may retrieve a first media command, set the DMA to copy data associated with the first media command to the first media circuit, and send the first media command to the first media circuit. While the first media command is being executed, the media managing circuit may also retrieve a second media command, determine that the second media command utilizes data that is dependent on a completion of the first media command, and set the DMA to copy data from the first media circuit to the second media circuit. After the first media command has been completed, the media managing circuit may also send the second media command to the second media circuit.

Abstract: A patient monitoring system includes a display that displays a plurality of sectors including one or more icons. A controller is configured to display patient data received from a patient monitoring system in a corresponding sector of the display. The controller programmed to determine patient status from the patient data and display the patient status as an icon on the display. The icon is color-coded with the severity or deviation from normal of the patient status. The icon can also include an arrow that indicates if the patient status is improving or deteriorating.

Abstract: A texture unit of a graphics processing unit (GPU) may receive a texture data. The texture unit may receive the texture data from the memory. The texture unit may also multiply, by a multiplier circuit of the texture unit, the texture data by at least one constant, where the constant is not associated with a filtering operation, and where the texture data comprises at least one texel. The texture unit may also output, by the texture unit, a result of multiplying the texture data by the at least one constant.