Patents Examined by Jordan Klein
  • Patent number: 10211225
    Abstract: A method including patterning a continuous fin having a first segment and a second segment in a semiconductor layer, the first segment is arranged at an angle relative to the second line segment, and forming a first gate and a second gate substantially parallel to each other, the first gate substantially covering sides and a top of a portion of the first segment of the continuous fin, the second gate substantially covering sides and a top of a portion of the second segment of the continuous fin.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Tenko Yamashita
  • Patent number: 10211281
    Abstract: In one embodiment, an isolation device has a substrate, a metal plate, a conductive layer, first and second isolation layers are disclosed. The conductive layer may be formed within the substrate. The conductive layer may be arranged coupled to the metal plate, so as to receive a capacitively coupled signal from the metal plate. The first and second isolation layers may be sandwiched between the metal plate and the conductive layer. In another embodiment, an isolation device comprising a semiconductor substrate, a topmost metal layer and a plurality of additional metal layers is disclosed. The isolation device further comprises an isolation capacitor formed using the topmost metal layer and a conductive layer coupled to at least one of the plurality of additional metal layers.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: February 19, 2019
    Assignee: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
    Inventors: Qian Tao, Fun Kok Chow
  • Patent number: 10192977
    Abstract: In the present application, a power semiconductor device includes a first-conductive-type first base region having a first principal surface and a second principal surface opposite to the first principal surface, a second-conductive-type second base region disposed on the first principal surface and at least three groove parts parallel to each other disposed from a surface of the second base region. The device further includes insulating films covering inner walls of the respective groove parts, conductive trench gates filled on the insulating films, a first-conductive-type emitter region disposed in the second base region, and a second-conductive-type collector region disposed on the second principal surface of the first base region. The trench gates embedded in the first groove part and the third groove part are electrically connected to the gate electrode, and the trench gate embedded in the second groove part is electrically connected to the emitter electrode.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: January 29, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akihiko Furukawa, Shoichi Orita, Hiroki Muraoka, Atsushi Narazaki, Tsuyoshi Kawakami, Yuji Murakami
  • Patent number: 10170634
    Abstract: A nanowire field effect transistor (FET) device includes a first source/drain region and a second source/drain region. Each of the first and second source/drain regions are formed on an upper surface of a bulk semiconductor substrate. A gate region is interposed between the first and second source/drain regions, and directly on the upper surface of the bulk semiconductor substrate. A plurality of nanowires are formed only in the gate region. The nanowires are suspended above the semiconductor substrate and define gate channels of the nanowire FET device. A gate structure includes a gate electrode formed in the gate region such that the gate electrode contacts an entire surface of each nanowire.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Jeffrey W. Sleight
  • Patent number: 10163868
    Abstract: A semiconductor device includes an insulating substrate having an insulating plate and a circuit plate; a semiconductor chip having a front surface provided with a gate electrode and a source electrode, and a rear surface fixed to the circuit plate; a printed circuit board facing the insulating substrate, and including a first metal layer and a second metal layer; a first conductive post having two ends electrically and mechanically connected to the gate electrode and the first metal layer; a second conductive post having two ends electrically and mechanically connected to the source electrode and the second metal layer; and a circuit impedance reducing element electrically connected between the gate electrode and the source electrode through the first conductive post and the second conductive post.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: December 25, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masafumi Horio, Yoshinari Ikeda, Hideyo Nakamura, Hayato Nakano
  • Patent number: 10164036
    Abstract: The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: December 25, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Tetsuya Watanabe, Mitsuru Miyamori, Katsumi Tsuneno, Takashi Shimizu
  • Patent number: 10153453
    Abstract: An electronic component includes a connection carrier having a cover surface, a first electric connection point and a second electric connection point, and an organic active area. A first electrode interconnects in an electrically conductive manner the active area and the first electric connection point. An encapsulation layer protects the active area against humidity and atmospheric gases. The electronic component can be contacted from the outside by the electric connection points and the encapsulation layer is in direct contact, in places, with the connection carrier.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: December 11, 2018
    Assignee: OSRAM OLED GmbH
    Inventors: Egbert Höfling, Simon Schicktanz
  • Patent number: 10153304
    Abstract: The present disclosure relates to a TFT includes an active layer formed on a substrate, wherein the active layer includes a first semiconductor layer and a second semiconductor layer stacked together. The first semiconductor layer is made by Indium gallium zinc oxide (IGZO) having an atomic ratio In/(Ga+Zn) smaller than 50%, and the second semiconductor layer is made by IGZO having the atomic ratio In/(Ga+Zn) greater than 55%. The present disclosure also includes an array substrate having the TFT and the manufacturing method thereof. The array substrate may be adopted in LCD or OLED. The TFT adopts two layers of IGZO semiconductor materials to be the semiconductor of the active layer. Not only the demand toward the TFT characteristics may be satisfied, but also the carrier mobility rate of the IGZO active layer may be enhanced.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: December 11, 2018
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd
    Inventor: Fang Qin
  • Patent number: 10134857
    Abstract: The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: November 20, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Tetsuya Watanabe, Mitsuru Miyamori, Katsumi Tsuneno, Takashi Shimizu
  • Patent number: 10134854
    Abstract: A high electron mobility transistor includes a substrate including a first surface and a second surface facing each other and having a via hole passing through the first surface and the second surface, an active layer on the first surface, a cap layer on the active layer and including a gate recess region exposing a portion of the active layer, a source electrode and a drain electrode on one of the cap layer and the active layer, an insulating layer on the source electrode and the drain electrode and having on opening corresponding to the gate recess region to expose the gate recess region, a first field electrode on the insulating layer, a gate electrode electrically connected to the first field electrode on the insulating layer, and a second field electrode on the second surface and contacting the active layer through the via hole.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: November 20, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Ho Kyun Ahn, Dong Min Kang, Yong-Hwan Kwon, Dong-Young Kim, Seong Il Kim, Hae Cheon Kim, Eun Soo Nam, Jae Won Do, Byoung-Gue Min, Hyung Sup Yoon, Sang-Heung Lee, Jong Min Lee, Jong-Won Lim, Hyun Wook Jung, Kyu Jun Cho
  • Patent number: 10134682
    Abstract: A module includes a circuit package having multiple electronic components on a substrate, a molded compound disposed over the substrate and the electronic components, and an external shield disposed on at least one outer surface of the circuit package. The external shield is segmented into multiple external shield partitions that are grounded, respectively. Adjacent external shield partitions of the multiple external shield partitions are separated by a corresponding gap located between adjacent electronic components of the multiple electronic components. The external shield is configured to protect the circuit package from external electromagnetic radiation and environmental stress. Each corresponding gap separating the adjacent external shield partitions is configured to provide internal shielding of at least one of the electronic components, between which the corresponding gap is located, from internal electromagnetic radiation generated by the other of the adjacent electronic components.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: November 20, 2018
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Nitesh Kumbhat, Deog Soon Choi, Ashish Alawani, Li Sun
  • Patent number: 10128196
    Abstract: A semiconductor device including: a semiconductor substrate a semiconductor element is formed; a first electrode layer stacked on the semiconductor substrate and connected to the semiconductor element; a first insulation film stacked on an upper face of the first electrode layer; and a second electrode layer stacked over the first electrode layer and the first insulation film, the second electrode layer including a material having a mechanical strength that is higher than a mechanical strength of a material included in the first electrode layer; wherein a groove portion is provided from the upper face in a direction toward a lower face of the first electrode layer, a protrusion portion protruding into the groove portion is provided on a lower face of the second electrode layer, and a lower end of the protrusion portion is positioned below the center position in a thickness direction of the first electrode layer.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: November 13, 2018
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Takashi Ushijima
  • Patent number: 10128208
    Abstract: In some embodiments, a package substrate for a semiconductor device includes a substrate core and a material layer disposed over the substrate core. The package substrate includes a spot-faced aperture disposed in the substrate core and the material layer.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: November 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hao-Cheng Hou, Yu-Feng Chen, Jung Wei Cheng, Yu-Min Liang, Tsung-Ding Wang
  • Patent number: 10128181
    Abstract: A package structure includes a first carrier plate, a second carrier plate, a pin group and an encapsulant member. A power component is disposed on a first top surface of the first carrier plate. The second carrier plate is disposed on the first top surface of the first carrier plate. A driving circuit is disposed on a second top surface of the second carrier plate for driving the power component. An opening runs through the second carrier plate, and the power component is accommodated within the opening. The pin group is assembled on the first carrier plate and/or the second carrier plate. The encapsulant member encapsulates the first carrier plate, the second carrier plate, a part of the first pin group and a part of the second pin group, so that the first pin group and the second pin group are partially exposed outside the encapsulant member.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: November 13, 2018
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventors: Kai Lu, Zhenqing Zhao, Tao Wang
  • Patent number: 10115909
    Abstract: The embodiments of the present invention provide an organic electroluminescent device, a manufacturing method thereof and an electronic equipment. The organic electroluminescent device comprises: an anode layer, a hole transport layer, a first light emitting layer, a second light emitting layer, an electron transport layer, and a cathode layer stacked in sequence; wherein the first light emitting layer and the second light emitting layer comprise a same substrate material; the first light emitting layer and/or the second light emitting layer are doped such that a hole mobility of the first light emitting layer is equal to an electron mobility of the second light emitting layer. In the embodiments of the present invention, two light emitting layers with the same substrate material are applied, which can realize a balanced injection for electrons and holes, thereby improving the efficiency and lifetime of the organic electroluminescent device.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: October 30, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Haidong Wu, Yun Qiu, Weilin Lai
  • Patent number: 10109588
    Abstract: An electronic component package includes a frame containing a metal or ceramic based material and having a through-hole, an electronic component disposed in the through-hole, an insulating part at least covering upper portions of the frame and the electronic component, a bonding part at least partially disposed between the frame and the insulating part, and a redistribution part disposed at one side of the frame and the electronic component.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: October 23, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sung Won Jeong, Young Gwan Ko, Myung Sam Kang, Tae Hong Min
  • Patent number: 10090485
    Abstract: An organic light emitting diode (OLED) display includes: a substrate including a plurality of organic light emitting elements; an adhesive member on at least a portion of an upper surface of the substrate; a flexible circuit board adhered to the upper surface of the adhesive member and having a portion bent to be mounted to a lower surface of the substrate; and a light blocking member at the upper surface of the substrate, wherein the light blocking member is laterally offset from the adhesive member.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: October 2, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Young-Min You, Dae-Kil Park
  • Patent number: 10079249
    Abstract: A method including patterning a continuous fin having a first segment and a second segment in a semiconductor layer, the first segment is arranged at an angle relative to the second segment, and forming a first gate and a second gate substantially parallel to each other, the first gate substantially covering sides and a top of a portion of the first segment of the continuous fin, the second gate substantially covering sides and a top of a portion of the second segment of the continuous fin.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Tenko Yamashita
  • Patent number: 10079259
    Abstract: An image sensor includes a semiconductor substrate, a plurality of photoelectric transducer devices, a dielectric isolating structure and a plurality of spacers. The semiconductor substrate has a backside surface and a front side surface opposite to the backside surface. The photoelectric transducer devices are disposed on the front side surface. The dielectric isolating structure extends downwards into the semiconductor substrate from the front side surface and penetrates through the backside surface, so as to from a grid structure and isolate the photoelectric transducer devices from each other. The spacers are disposed on a plurality of sidewalls of the grid structure.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: September 18, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Chung Yu, Kai-Chieh Chuang
  • Patent number: 10068922
    Abstract: A continuous fin having a first segment and a second segment in a semiconductor layer, the first segment is arranged at an angle relative to the second segment, and a first gate and a second gate substantially parallel to each other, the first gate substantially covering sides and a top of a portion of the first segment of the continuous fin, the second gate substantially covering sides and a top of a portion of the second segment of the continuous fin.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Tenko Yamashita