Abstract: The present disclosure provides a power module with the integration of a control circuit at least, including: a power substrate; a power device mounted on the power substrate; and at least one control substrate which supports the control circuit, is electrically connected with the power substrate and disposed at an angle of inclination on a surface of the power substrate on which the power device is mounted; wherein the angle of inclination is greater than or equal to 45 degrees and smaller than or equal to 135 degrees. In the power module provided by the present disclosure, only the power substrate as well as the connections between the control substrate and the power substrate occupies the footprint area of the power module, and thus the horizontal footprint area of the power module is effectively reduced and thereby the power density of the power module is increased.

Abstract: An imaging device with high imaging quality capable of being manufactured at low cost is provided. The imaging device includes a first transistor, a second transistor, a third transistor, a fourth transistor, a photodiode, and a capacitor. Each of the first to the fourth transistors includes a first gate electrode and a second gate electrode, and the second gate electrode of each of the first to the fourth transistors and one electrode of the capacitor are electrically connected to an anode electrode of the photodiode.

Abstract: A structure and method for forming a substrate, a buffer layer disposed on the substrate, an oxide layer disposed on the buffer layer, and a fin comprising a semiconductor material disposed on the oxide layer.

Abstract: Embodiments are directed to a magnetic tunnel junction (MTJ) memory cell that includes a reference layer formed from a perpendicular magnetic anisotropy (PMA) reference layer and an interfacial reference layer. The MTJ further includes a free layer and a tunnel barrier positioned between the interfacial reference layer and the free layer. The tunnel barrier is configured to enable electrons to tunnel through the tunnel barrier between the interfacial reference layer and the free layer. A first in-situ alignment is provided between a tunnel barrier lattice structure of the tunnel barrier and an interfacial reference layer lattice structure of the interfacial reference layer. A second in-situ alignment is provided between the tunnel barrier lattice structure of the tunnel barrier and a free layer lattice structure of the free layer. The PMA reference layer lattice structure is not aligned with the interfacial reference layer lattice structure.

Abstract: A flexible array substrate structure and manufacturing method thereof are disclosed, in which the patterning process of an organic semi-conductive layer is achieved by using the inside wall of the opening of a color film layer as a bank, so that one mask can be saved. Also, a process for manufacturing a device can be simplified by an improved device structure, so that the flexible array substrate structure of the invention can be obtained by only using four masks.

Abstract: The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.

Abstract: An electronic package includes a substrate having opposing first and second surfaces. Conductive areas are on a first surface of the substrate and include at least one edge conductive area. A plurality of conductive bumps are on the second surface of the substrate and coupled to respective ones of the conductive areas. An integrated circuit (IC) is carried by the substrate. Bond wires are coupled between the IC and respective ones of the conductive areas. An encapsulating material is over the IC and adjacent portions of the substrate. A conductive layer is on the encapsulating material, and at least one conductive body is coupled between the at least one edge conductive area and the conductive layer.

Abstract: Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET) device. The method includes forming at least one source region having multiple sides, forming at least one drain region having multiple sides, forming at least one channel region having multiple sides, forming at least one gate region around the multiple sides of the at least one channel region and forming the at least one gate region around the multiple sides of the at least one drain region.

Abstract: Embodiments are directed to a method of forming portions of a fin-type field effect transistor (FinFET) device. The method includes forming at least one source region having multiple sides, forming at least one drain region having multiple sides, forming at least one channel region having multiple sides, forming at least one gate region around the multiple sides of the at least one channel region and forming the at least one gate region around the multiple sides of the at least one drain region.

Abstract: An interdigitated capacitor includes a substrate and a pair of comb-like electrodes both formed on the semiconductor substrate and horizontally arranged thereon, each of the pair of comb-like electrodes including finger electrodes having a curved profile.

Abstract: A semiconductor device is provided. The semiconductor device may include stacks including conductive layers and insulating layers. The conductive layers and insulating layers may be alternately stacked. The semiconductor device may include semiconductor patterns passing through the stacks. The semiconductor device may include plug patterns located on the semiconductor patterns and protruding compared to the stacks. The semiconductor device may include insulating patterns located on the stacks and the plug patterns and each including an edge area having a height at a level lower than a central area. The semiconductor device may include slit insulating layers located between the stacks and between the insulating patterns.

Abstract: A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.

Abstract: A light emitting device is provided to include an n-type semiconductor layer, a p-type semiconductor layer, an active layer, and an electron blocking layer disposed between the p-type semiconductor layer and the active layer. The p-type semiconductor layer includes a hole injection layer, a p-type contact layer, and a hole transport layer. The hole transport layer includes a plurality of undoped layers and at least one intermediate doped layer disposed between the undoped layers. At least one of the undoped layers includes a zone in which hole concentration decreases with increasing distance from the hole injection layer or the p-type contact layer, and the intermediate doped layer is disposed to be at least partially overlapped with a region of the hole transport layer, the region having the hole concentration of 62% to 87% of the hole concentration of the p-type contact layer.

Abstract: A device includes a substrate feature disposed over a substrate. The substrate feature has a first length extending along a first direction and a second length extending along a second direction. The first length is greater than the second length. The device also includes a first material feature disposed over the substrate. The first material feature has a first surface in physical contact with the substrate feature and a second surface opposite to the first surface. The first surface has a third length extending along the first direction and a fourth length extending along the second direction. The third length is greater than the fourth length. The second surface has a fifth length extending along the first direction and a sixth length extending along the second direction. The sixth length is greater than the fifth length.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack to the substrate. After formation of memory film layers, a sacrificial cover material layer can be employed to protect the tunneling dielectric layer during formation of a bottom opening in the memory film layers. An amorphous semiconductor material layer can be deposited and optionally annealed in an ambient including argon and/or deuterium to form a semiconductor channel layer having a thickness less than 5 nm and surface roughness less than 10% of the thickness. Alternately or additionally, at least one interfacial layer can be employed on either side of the amorphous semiconductor material layer to reduce surface roughness of the semiconductor channel. The ultrathin channel can have enhanced mobility due to quantum confinement effects.

Abstract: A method of manufacturing a semiconductor device includes forming a first via having a first diameter in a first main surface of a semiconductor substrate having a first thickness, after forming a first insulating film on a bottom surface and a side surface of the first via, forming a first through electrode inside the first via a first barrier metal film, after forming the first through electrode, processing the semiconductor substrate from a second main surface on an opposite side of the first main surface to reduce the first thickness of the semiconductor substrate to a second thickness thinner than the first thickness, after processing the semiconductor substrate, forming a third insulating film on the second main surface of the semiconductor substrate, and after forming the third insulating film, sequentially processing the third insulating film and the semiconductor substrate.

Abstract: A silicon carbide substrate having a gate insulating film provided in contact with a first main surface, having a gate electrode provided in contact with the gate insulating film, and having a source region exposed from first main surface is prepared. A first recess having a first inner wall surface is formed in an interlayer insulating film by performing a first isotropic etching with respect to the interlayer insulating film with use of a mask layer. A second recess having a second inner wall surface is formed by performing a first anisotropic etching with respect to the interlayer insulating film and the gate insulating film with use of the mask layer and thereby exposing the source region from gate insulating film. An interconnection is formed which is arranged in contact with the first inner wall surface and the second inner wall surface and electrically connected to a source electrode.

Abstract: Forming a set of semiconductor fins is disclosed. Forming the set of semiconductor fins can include forming a base structure including a silicon substrate, an insulator layer stacked on the silicon substrate, and a plurality of silicon semiconductor fins each stacked directly on the insulator layer. Forming the set of semiconductor fins can include depositing a first atomic layer of germanium atoms on a first set of semiconductor fins in the plurality of semiconductor fins and annealing the first atomic layer and the first set of semiconductor fins. Forming the set of semiconductor fins can include forming, from the annealing, a first set of silicon-germanium semiconductor fins.

Abstract: In some embodiments, a nitride film is provided over a semiconductor substrate and densified. The nitride film may be a flowable nitride, which may be deposited to at least partially fill openings in the substrate. Densifying the film is accomplished without exposing the nitride film to plasma by exposing the nitride film to a non-plasma densifying agent in the process chamber. The non-plasma densifying agent may be a nitriding gas, a hydrogen scavenging gas, a silicon precursor, or a combination thereof.

Abstract: A semiconductor device with an anti-pad peeling structure is disclosed. The semiconductor device includes: a semiconductor substrate including a Through Substrate Via (TSV); a dielectric layer on the semiconductor substrate and including a plurality of recesses therein; and a pad above the semiconductor substrate to cover a portion of the dielectric layer and extend to the recesses; wherein the pad extends to the plurality of recesses, and a plurality of contact points are confined in the recesses between the pad and the conductive layer, and each of the contact points is at least partially excluded from a boundary of the TSV when being seen from a top-down perspective.