Abstract: A method of integrating at least one passive component and at least one active power device on a same substrate includes: forming a substrate having a first resistivity value associated therewith; forming a low-resistivity region having a second resistivity value associated therewith in the substrate, the second resistivity value being lower than the first resistivity value; forming the at least one active power device in the low-resistivity region; forming an insulating layer over at least a portion of the at least one active power device; and forming the at least one passive component on an upper surface of the insulating layer above the substrate having the first resistivity value, the at least one passive component being disposed laterally relative to the at least one active power device and electrically connected with the at least one active power device.

Abstract: A manufacturing method for an organic electroluminescent device disposes a scattering layer between a substrate and an anode. The scattering layer is made of a titanium dioxide film, and the titanium dioxide film is formed by an electrospinning process. The density and thickness of an electrospun membrane can be adjusted through a voltage and a distance between electrodes during the electrospinning process. The process parameters are easy to be adjusted and operability is increased to effectively improve a light efficiency. When a light exit from the anode and enter into the substrate inside the device, the scattering layer will scatter the light to change a light path within a critical angle of a total reflection in order to reduce an incident angle. Accordingly, a light which is supposed to be total reflected will be refracted so as to improve the light efficiency.

Abstract: Systems and methods are provided for annealing a semiconductor structure. In one embodiment, the method includes providing an energy-converting structure proximate a semiconductor structure, the energy-converting structure comprising a material having a loss tangent larger than that of the semiconductor structure; providing a heat reflecting structure between the semiconductor structure and the energy-converting structure; and providing microwave radiation to the energy-converting structure and the semiconductor structure. The semiconductor structure may include at least one material selected from the group consisting of boron-doped silicon germanium, silicon phosphide, titanium, nickel, silicon nitride, silicon dioxide, silicon carbide, n-type doped silicon, and aluminum capped silicon carbide. The heat reflecting structure may include a material substantially transparent to microwave radiation and having substantial reflectivity with respect to infrared radiation.

Abstract: This disclosure provides a negative capacitance gate stack structure with a variable positive capacitor to implement a hysteresis free negative capacitance field effect transistors (NCFETs) with improved voltage gain. The gate stack structure provides an effective ferroelectric negative capacitor by using the combination of a ferroelectric negative capacitor and the variable positive capacitor with semiconductor material (such as polysilicon), resulting in the effective ferroelectric negative capacitor's being varied with an applied gate voltage. Our simulation results show that the NCFET with the variable positive capacitor can achieve not only a non-hysteretic ID-VG curve but also a better sub-threshold slope.

Abstract: An electrostatic discharge (ESD) device for an integrated circuit includes a substrate having a longitudinally extending fin dispose thereon. A first n-type FinFET (NFET) is disposed within the fin. The NFET includes an n-type source, an n-type drain and a p-well disposed within the substrate under the source and drain. A p-type FinFET (PFET) is disposed within the fin. The PFET includes a p-type source/drain region and an n-well disposed within the substrate under the source/drain region. The n-well and p-well are located proximate enough to each other to form an np junction therebetween. The p-type source/drain region of the PFET and the n-type drain of the NFET are electrically connected to a common input node.

Abstract: A NAND memory is provided that includes a memory cell region and a peripheral region. The peripheral region includes a shallow trench isolation trench disposed in a substrate. The shallow trench isolation trench includes a first top surface, and a second top surface. A difference between a height of the second top surface and a height of the first top surface is less than a predetermined value ?MAX.

Abstract: A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.

Abstract: The invention relates to an electrical device comprising an electrical unit (2) like an organic light emitting diode, a protection element (3) like a thin film encapsulation, which at least partly covers the electrical unit, for protecting the electrical unit against water and/or oxygen, and a detection layer (4) arranged between the protection element and the electrical unit or within the protection element, wherein the detection layer comprises organic material and is adapted such that a property of the detection layer is changed, if the detection layer is in contact with a contact gas usable for detecting a permeability of the protection element. This allows easily integrating a fast detection test for detecting a permeability of the protection element into a production process for producing the electrical device, i.e. a time consuming external permeability test may not be required.

Abstract: In various embodiments of the present disclosure, there is provided a method of manufacturing a monolayer graphene photodetector, the method including forming a graphene quantum dot array in a graphene monolayer, and forming an electron trapping center in the graphene quantum dot array. Accordingly, a monolayer graphene photodetector is also provided.

Abstract: The semiconductor device including: two fins having rectangular parallelepiped shapes arranged in parallel in X-direction; and a gate electrode arranged thereon via a gate insulating film and extending in Y-direction is configured as follows. First, a drain plug is provided over a drain region located on one side of the gate electrode and extending in Y-direction. Then, two source plugs are provided over a source region located on the other side of the gate electrode and extending in Y-direction. Also, the drain plug is arranged in a displaced manner so that its position in Y-direction may not overlap with the two source plugs. According to such a configuration, the gate-drain capacitance can be made smaller than the gate-source capacitance and a Miller effect-based circuit delay can be suppressed. Further, as compared with capacitance on the drain side, capacitance on the source side increases, thereby improving stability of circuit operation.

Abstract: An organic light emitting diode (OLED) display includes: a substrate including a plurality of organic light emitting elements; an adhesive member on at least a portion of an upper surface of the substrate; a flexible circuit board adhered to the upper surface of the adhesive member and having a portion bent to be mounted to a lower surface of the substrate; and a light blocking member at the upper surface of the substrate, wherein the light blocking member is laterally offset from the adhesive member.

Abstract: A power transistor includes a number of transistor cells. Each transistor cell includes a source region, a drain region, a body region and a gate electrode. Each source region is arranged in a first semiconductor fin of a semiconductor body. Each drain region is at least partially arranged in a second semiconductor fin of the semiconductor body. The second semiconductor fin is spaced from the first semiconductor fin in a first horizontal direction of the semiconductor body. Each gate electrode is arranged in a trench adjacent the first semiconductor fin, is adjacent the body region, and is dielectrically insulated from the body region by a gate dielectric. Each of the first and second semiconductor fins has a width in the first horizontal direction and a length in a second horizontal direction, wherein the length is larger than the width.

Abstract: A substrate-less display device is disclosed. The substrate-less display device includes a barrier stack. The barrier stack includes a plurality of inorganic barrier films and a plurality of polymer films. The inorganic barrier films and the polymer films are alternatively disposed. The substrate-less display device further includes a thin-film-transistor (TFT) device layer disposed on the barrier stack, a display medium layer disposed on the TFT device layer, and an encapsulation layer disposed on the display medium layer.

Abstract: An IC structure including: a first replacement gate stack for the pFET, the first replacement gate stack including: an interfacial layer in a first opening in the dielectric layer; a high-k layer over the interfacial layer in the first opening; a pFET work function metal layer over the high-k layer in the first opening; and a first gate electrode layer over the pFET work function metal layer and substantially filling the first opening; and a second replacement gate stack for the nFET, the second gate stack laterally adjacent to the first gate stack and including: the interfacial layer in a second opening in the dielectric layer; the high-k layer over the interfacial layer in the second opening; a nFET work function metal layer over the high-k layer in the second opening; and a second gate electrode layer over the nFET work function metal layer and substantially filling the second opening.

Abstract: A method comprises providing a semiconductor structure including a nonvolatile memory cell element comprising a floating gate, a select gate and an erase gate formed over a semiconductor material, the select gate and the erase gate being arranged at opposite sides of the floating gate, forming a control gate insulation material layer over the semiconductor structure, forming a control gate material layer over the control gate insulation material layer, performing a first patterning process that forms a control gate over the floating gate and comprises a first etch process that selectively removes a material of the control gate material layer relative to a material of the control gate insulation material layer, and performing a second patterning process that patterns the control gate insulation material layer, the patterned control gate insulation material layer covering portions of the semiconductor structure that are not covered by the control gate.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes: providing a workpiece having a recess and a dielectric layer lining the recess; forming a conductive structure within the recess, wherein the conductive structure partially fills the recess; and recessing the dielectric layer, wherein, after the recessing, a top surface of the recessed dielectric layer is disposed within the recess.

Abstract: A system and method for forming a sensor device includes defining an in-plane electrode in a device layer of a silicon on insulator (SOI) wafer, forming an out-of-plane electrode in a silicon cap layer located above an upper surface of the device layer, depositing a silicide-forming metal on a top surface of the silicon cap layer, and annealing the deposited silicide-forming metal to form a silicide portion in the silicon cap layer.

Abstract: An electronic component includes an electrically conductive carrier. The electrically conductive carrier includes a carrier surface and a semiconductor chip includes a chip surface. One or both of the carrier surface and the chip surface include a non-planar structure. The chip is attached to the carrier with the chip surface facing towards the carrier surface so that a gap is provided between the chip surface and the carrier surface due to the non-planar structure of one or both of the carrier surface and the first chip surface. The electronic component further includes a first galvanically deposited metallic layer situated in the gap.

Abstract: A device includes a metal pad, a passivation layer overlapping edge portions of the metal pad, and a first polymer layer over the passivation layer. A Post-Passivation-Interconnect (PPI) has a level portion overlying the first polymer layer, and a plug portion that has a top connected to the level portion. The plug portion extends into the first polymer layer. A bottom surface of the plug portion is in contact with a dielectric material. A second polymer layer is overlying the first polymer layer.

Abstract: A method of a semiconductor package includes providing a substrate having a conductive trace coated with an organic solderability preservative (OSP) layer, removing the OSP layer from the conductive trace, and then coupling a chip to the substrate to form a semiconductor package.