Patents Examined by José H. Alcalá
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Patent number: 6392158Abstract: A stack including a micro-system having an electrical contact to connect the micro-system to the outside world, a substrate having a first layer formed on the substrate, a through hole extending in an axial direction of the substrate and configured to reveal a rear side of the first layer and to provide a passage to electrically connect to the electrical contact, and a cavity located at an end of the through hole close to the first layer, wherein the cavity has dimensions transverse to the axial direction larger than a diameter of the through hole and forms an overhanging edge around the through hole.Type: GrantFiled: August 8, 2000Date of Patent: May 21, 2002Assignee: Commissariat a l'Energie AtomiqueInventors: Stéphane Caplet, Marie-Thérèse Delaye
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Patent number: 6384340Abstract: A multi-layer circuit board includes first, second, third, fourth and fifth insulating substrates, first, second, third and fourth signal wiring layers, a ground wiring layer, and a power wiring layer. The insulating substrates and the wiring layers are press-bonded to each other to form the circuit board with a thickness of about 1.2 mm. Each of the first and fifth insulating substrates has a thickness ranging from 4.175 to 4.725 mil. Each of the second and fourth insulating substrates has a thickness ranging from 5.7 to 6.3 mil. The third insulating substrate has a thickness ranging to 16.8 mil.Type: GrantFiled: March 6, 2001Date of Patent: May 7, 2002Assignee: Mitac International Corp.Inventor: Yu-Chiang Cheng
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Patent number: 6380493Abstract: To provide a circuit board, having a circuit pattern of adequate high-frequency characteristics, for transmitting high-frequency electric signals at high speed, a circuit board, including a base layer formed of insulating material and a conductive layer formed on the base layer in the form of a specified circuit pattern, is so constructed that an air layer is made to lie between lines of wire of the circuit pattern or is so constructed that the lines of wire are covered with the cover layer but land portions of the base layer extending between the lines of wire are not covered with the cover layer. This construction of the invention enables dielectric constant between the lines of wire to be reduced and, as a result of this, the capacitance between the lines of wire can be reduced to provide improved high-frequency characteristics of the circuit pattern.Type: GrantFiled: October 26, 2000Date of Patent: April 30, 2002Assignee: Nitto Denko CorporationInventors: Shigenori Morita, Yasuhito Ohwaki, Tadao Ohkawa, Toshihiko Omote
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Patent number: 6376779Abstract: A printed circuit board having a plurality of spaced apart scrap border support tabs along the perimeter. The board surfaces including the edges are coated with a conductive shielding material, except that each tab presents an uncoated, unshielded surface at the point of severance created by detachment of a scrap border subsequent to the coating application. The printed circuit board includes a plurality of spaced apart elongated apertures adjacent the perimeter, with each aperture being inwardly coincident to a respective one of each support tabs, each aperture defining an inner surface adjacent to the corresponding support tab with a portion of the inner surface being substantially parallel to adjacent perimeter portions of the circuit board, the inner surface of each aperture also being coated with the conductive shielding material with the latter being attached to the conductive shielding material of the board surface.Type: GrantFiled: August 24, 2000Date of Patent: April 23, 2002Assignee: Nortel Networks LimitedInventors: Simon E. Shearman, Geoffrey G. Skanes, Kyle G. Edginton, Denis Kasprowicz
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Patent number: 6362433Abstract: A flexible printed circuit board that is intended to minimize curling is formed having a first polyimide-resin layer with a conductor pattern formed on one surface thereof and supporting that conductor pattern. A second polyimide-resin is formed on another surface of the conductor pattern and covers and protects the circuit of the conductor pattern. The polyimide-resin layers are chosen so that a difference between a coefficient of linear thermal expansion of the first polyimide-resin layer and the coefficient of linear thermal expansion of the second polyimide-resin layer is 3×10−6/K or smaller.Type: GrantFiled: June 4, 1999Date of Patent: March 26, 2002Assignee: Sony Chemicals CorporationInventors: Satoshi Takahashi, Akira Tsutsumi, Noriaki Kudo, Akihiro Arai, Koji Arai, Koichi Uno, Satoshi Oaku, Osamu Ichihara, Hiromasa Ota
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Patent number: 6362438Abstract: The present invention provides a circuit board with a plated-through hole, wherein a first end of the plated-through hole is electrically attached to a cap formed of conductive material. One or more surface pads terminate on a surface layer of the printed circuit board, and are connected to the cap by one or more vias extending from the cap to the one or more surface pads. In some embodiments, the circuit board is a substrate for mounting an integrated circuit, such as a ball-grid array integrated circuit. The invention includes methods for making the novel circuit board, as well as integrated circuit assemblies comprising the novel circuit board with an integrated circuit mounted thereto.Type: GrantFiled: December 15, 1999Date of Patent: March 26, 2002Assignee: Intel CorporationInventors: Tee Onn Chong, Chris Baldwin, Chee-Yee Chung
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Patent number: 6348661Abstract: In the manufacture of disk drive suspension flexures, an absence of exposed unplated conductive trace ends at the locus of severing individual flexures from a panel of flexures is achieved by reducing the cross section a portion of the conductive traces at the locus of severing so that the portion preferentially melts upon passage of a current through the conductive traces, severing the portion and encasing the severed ends in melted plastic from the flexure plastic film layer.Type: GrantFiled: September 1, 2000Date of Patent: February 19, 2002Assignee: Magnecomp Corp.Inventor: Warren Coon
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Patent number: 6337796Abstract: A semiconductor device mount structure includes a heat dissipating member, a circuit board, a semiconductor device and a leaf spring member. The heat dissipating member has a mounting surface. The circuit board is opposed to the mounting surface of the heat dissipating member. The semiconductor device is mounted to the mounting surface of the heat dissipating member. The semiconductor device is electrically connected to the circuit board. The leaf spring member is arranged between the semiconductor device and the circuit board in such a manner that the leaf spring member biases the semiconductor device against the mounting surface of the heat dissipating member. The leaf spring member has a heat insulating material integrated on one side thereof which faces the circuit board.Type: GrantFiled: May 11, 2001Date of Patent: January 8, 2002Assignee: Denso CorporationInventors: Masao Yamada, Shinichi Konda, Taketoshi Sato
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Patent number: 6335495Abstract: An electrical structure, comprising a first dielectric layer, a patterned layer on the first dielectric layer, and a second dielectric layer on the patterned layer. The patterned layer includes a metal pattern on the first dielectric layer, a metallic pattern on the metal pattern, and a plugged pattern within a remaining space of the patterned layer. The plugged pattern includes a dielectric material. The second dielectric layer is adhesively bonded to a top surface of the patterned layer. The second dielectric layer includes the dielectric material.Type: GrantFiled: June 29, 1999Date of Patent: January 1, 2002Assignee: International Business Machines CorporationInventors: Donald S. Farquhar, Edmond O. Fey, Elizabeth F. Foster, Michael J. Klodowski
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Patent number: 6335494Abstract: Power layers of a multi-layer connection structure forming a power distribution network are partitioned to accommodate all necessary voltages for one or more chips connected thereto in each power layer. By doing so, and rearranging vias as permitted by such partitioning via length is reduced while via numbers can be increased to reduce self-inductance of the structure. Transmission lines formed by conductors in the signal layers are referenced to the correct power supply and return/image currents are made of similar path length and substantially symmetrical for both positive- and negative-going signal transitions. These effects reduce delta-I noise to levels which preserve good signal-to-noise ratios to current and foreseeable reduced signal levels.Type: GrantFiled: June 23, 2000Date of Patent: January 1, 2002Assignee: International Business Machines CorporationInventors: Roger P. Gregor, James P. Libous
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Patent number: 6333472Abstract: A circuit board (1) for use in a connector between cables of a data transmission system has at least one array of input terminals (T1-T8) for incoming signals, at least one array of output terminals (t1-t8) for outgoing signals, and a respective conductive track (5) connecting each input terminal to a respective output terminal. Closed loops (6, 7, 8) of conductive material are connected to at least some of the terminals or conductive tracks, the loops being positioned on the circuit board to reduce crosstalk from the levels which would exist within the connector in the absence of such closed loops. The loops associated with one terminal will be positioned on the board opposite loops associated with another terminal or terminals to produce coupling therebetween. The invention is particularly applicable to RJ45 plug and jack systems.Type: GrantFiled: December 4, 2000Date of Patent: December 25, 2001Inventor: Richard Weatherley
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Patent number: 6331118Abstract: An electrode spacing conversion adaptor is formed of a plurality of sheet elements having top and bottom electrodes arrayed at different intervals along upper and lower ends of each sheet element, respectively, wherein the top electrodes are individually connected to their corresponding bottom electrodes by intermediate conductors. The individual sheet elements are angled such that the upper portions of the sheet elements carrying the top electrodes are stacked at intervals different from intervals at which the lower portions carrying the bottom electrodes are stacked. The individual sheet elements may be stacked to form laminated pieces in such a way that the bottom electrodes are concentrated in a small area while the top electrodes are distributed over a larger area at greater intervals in two horizontal directions.Type: GrantFiled: June 17, 1999Date of Patent: December 18, 2001Assignee: Kabushiki Kaisha Linear CircuitInventors: Hiroaki Ono, Masanori Hirano
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Patent number: 6326556Abstract: Multilayer printed wiring board capable of effectively solving the swelling of the conductor layer resulting from residual solvent and lowering of adhesion property between a resin insulating layer and a conductor. The multilayer printed wiring board can be formed by laminating resin insulating layers and conductor layers on a substrate, wherein, among conductor layers at least constituted with signal layer and power layer, a conductor pattern of the power layer is of lattice-shaped form.Type: GrantFiled: June 11, 1999Date of Patent: December 4, 2001Assignee: Ibiden Co., Ltd.Inventors: Motoo Asai, Akihito Nakamura
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Patent number: 6326557Abstract: A multi-layer circuit board includes first, second, third, fourth and fifth insulating substrates, first, second, third and fourth wiring layers, a ground wiring layer and a power wiring layer. The insulating substrates and the wiring layers are press-bonded to each other to form the circuit board with a thickness of about 1.6 mm. Each of the first and fifth insulating substrates has a thickness of 5.7±0.285 mil. Each of the second and fourth insulating substrates has a thickness of 8±0.4 mil. The third insulating substrate has a thickness of 24.6±1.23 mil. The first signal wiring layer has a first resistance with respect to the ground wiring layer. The second signal wiring layer has a second resistance with respect to the ground wiring layer and the power wiring layer. The third signal wiring layer has a third resistance with respect to the ground wiring layer and the power wiring layer. The fourth signal wiring layer has a fourth resistance with respect to the power wiring layer.Type: GrantFiled: March 6, 2001Date of Patent: December 4, 2001Assignee: Mitac International Corp.Inventor: Yu-Chiang Cheng
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Patent number: 6323438Abstract: A semiconductor device with a dummy wiring pattern. The semiconductor device is capable of stabilizing the adhesively bonding state of a semiconductor element in which a semiconductor element is mounted on the printed circuit board. The printed circuit board includes a wiring pattern and an element mounting portion on which the semiconductor element is to be mounted and is fixed using an adhesive, wherein a dummy wiring pattern having a thickness nearly equal to that of the wiring pattern is provided on the element mounting portion and the semiconductor element is mounted on the dummy wiring pattern via the adhesive.Type: GrantFiled: June 9, 1999Date of Patent: November 27, 2001Assignee: Sony CorporationInventor: Hitoshi Ito
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Patent number: 6316733Abstract: A component for use in manufacturing printed circuits that in a finished printed circuit constitutes a functional element. The component is comprised of a film substrate formed of a first polymeric material having a first side and a second side. At least one layer of a tiecoat metal is applied to the first side of the film substrate. At least one layer of copper on the at least one layer of a tiecoat metal, the layer of copper having an essentially uncontaminated exposed surface facing away from the at least one layer of tiecoat metal. A plurality of spaced apart, adhesion promoting areas of a tiecoat metal are provided on the second side of the film substrate defining regions of exposed polymeric material on the second side of the film substrate.Type: GrantFiled: August 18, 2000Date of Patent: November 13, 2001Assignee: GA-TEK Inc.Inventors: Michael A. Centanni, Mark Kusner
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Patent number: 6313413Abstract: The substrate of the present invention mainly includes a plurality of bonding pads, a plurality of ball pads, a plurality of traces, a plurality of holes, a first wire and a second wire. The bonding pads and ball pads are located on a first surface of the substrate and are connected to one another by the traces. The first wire is arranged at the edge of the first surface of the substrate, the second wire is arranged at a slot area of a second surface of the substrate which is adhesively covered by a solder mask and further has two ends connecting to the first wire. The holes connect the first surface to the second surface. The traces are connected the bonding pads and ball pads of the first surface by passing through the corresponding holes and a slot area to the second wire of the second surface to form closed loops. In the slot area, the solder mask adhesively covers the traces.Type: GrantFiled: October 8, 1999Date of Patent: November 6, 2001Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Kun-Ching Chen, Yire-Zine Lee, Yung-I Yeh, Su Tao
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Patent number: 6291779Abstract: A high density printed wiring board is prepared by applying an essentially solid material into plated through holes such that the metallized layers within the through hole are unaffected by chemical metal etchants. In this manner, lateral surface metallized layers can exclusively be reduced in thickness by use of said chemical agents. These thinned lateral surface metallized layers are ultimately converted into fine pitch, 25 to 40 microns, circuitry, thereby providing high density boards. Since the through hole wall metallization is unaffected by the etching process, excellent electrical connection between the fine line circuitry is obtained. Various printed wiring board embodiments are also presented.Type: GrantFiled: June 30, 1999Date of Patent: September 18, 2001Assignee: International Business Machines CorporationInventors: Kenneth J. Lubert, Curtis L. Miller, Thomas R. Miller, Robert D. Sebesta, James W. Wilson, Michael Wozniak
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Patent number: 6284982Abstract: A component for use in forming a multi-layer printed circuit comprised of a film substrate formed of a first polymeric material. At least one layer of a flash metal is applied to a first side of the film substrate, and at least one layer of copper is applied on the layer of flash metal. A discrete area of a resistive material is disposed on a second side of the film substrate.Type: GrantFiled: August 18, 2000Date of Patent: September 4, 2001Assignee: GA-TEK Inc.Inventors: Mark Kusner, Michael A. Centanni
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Patent number: 6268569Abstract: A high-performance printed wiring board assembly is disclosed which utilizes a substrate component having a reinforcement material. The substrate has a glass fabric reinforcement embedded in a condensation-reacted and thermally-crosslinked nadic end-capped polyimide resin. There are electrically conductive lamina current pathways directly adhered to the substrate. There are high-temperature soldered or metallurgically bonded connections that electrically join conductor leads of electrical devices to the lamina current pathways.Type: GrantFiled: June 30, 1999Date of Patent: July 31, 2001Assignee: National Center for Manufacturing SciencesInventors: Daniel Anthony Scola, Richard Thomas Grannells