Abstract: Test terminals connected to output lead sections are divided into blocks, and in each of the blocks, an outermost pair of the test terminals extends inwards from the output lead sections to oppose each other, and the pair is located relatively far from a place where a liquid crystal driver LSI chip is mounted.

Abstract: Interconnecting substrates used in the manufacturing of microelectronic devices and printed circuit assemblies, packaged microelectronic devices having interconnecting substrates, and methods of making and using such interconnecting substrates. In one aspect of the invention, an interconnecting substrate comprises a first external layer having a first external surface, a second external layer having a second external surface, and a conductive core between the first and second external layers. The conductive core can have at least a first conductive stratum between the first and second external layers, and a dielectric layer between the first conductive stratum and one of the first or second external layers. The conductive core can also include a second conductive stratum such that the first conductive stratum is on a first surface of the dielectric layer and the second conductive stratum is on a second surface of the dielectric layer.

Abstract: A via plug layout structure for connecting different metallic layers. The structure includes a plurality of via plugs arranged in a fan-shaped pattern and a plurality of empty bars positioned between a single via plug and the fanned-out via plugs so that incoming current to the single via plug is equally distributed to every one of the fanned-out via plug and current stress in each fanned-out via plug is identical. Hence, via plugs having particularly serious electromigration problem can be discovered. In addition, single via plug having different critical dimension can be fabricated so that maximum critical dimension sustainable by the via plug is determined after an electromigration test.

Abstract: A low temperature co-fired ceramic substrate structure has first and second conductive patterns respectively disposed on first and second dielectric layers with the conductive patterns being separated by the first dielectric layer. The first conductive pattern has a first conductive element functioning as a first plate of a capacitor and a second conductive element functioning as a voltage potential lead for an integrated circuit device. The second conductive pattern is positioned below the first conductive pattern and functions as the second plate of the capacitor and as a thermally conductive heat transfer layer for the integrated circuit device. At least a first thermally conductive via is formed between the top and bottom surfaces of the second dielectric layer and below the second conductive element with the via thermally coupled to the second conductive pattern. The thermal via or vias may be thermally coupled to a heat sink disposed adjacent to the bottom surface of the second dielectric layer.

Abstract: The present invention provides a semiconductor device of the BGA configuration comprising: a wiring layer 2 arranged on a circuit substrate 1 via an insulation layer; a land metal portion 2 formed on the wiring layer 2; a solder resist 4 layered so as to cover the land metal excluding a center portion thereof and the entire surface of the circuit substrate 1; and a solder ball 5 arranged on the land metal portion defined and surrounded by the solder resist 4; wherein the land metal portion 3 has a solder ball contact surface having a groove (or a line-shaped protrusion) 7 extending continuously.

Abstract: An electrical distribution center has a circuit board interposed between an upper housing and a lower housing. The upper housing has a panel provided with a universal cavity design by a multiplicity of terminal-receiving slots. The slots are arranged in laterally spaced parallel rows with the slots in each row in equally spaced apart relation to one another. Raised rails on the top side of the panel are parallel to the rows of slots and respectively occupy the spaces between the rows of slots. The circuit board has terminals extending into selected slots through the bottom side of the panel. The slots are adapted to receive the terminals of relays and fuses inserted through the top side of the panel for contact with the terminals of the circuit board. When the terminals of a relay are inserted in any of the slots, the relay body will be supported on rails on opposite sides of those slots.

Abstract: A non-contact type IC card includes an insulating film having first and second surfaces. A plane coil is arranged on the first surface of the film. A semiconductor element is arranged on the first surface of the filmy The film has through holes which expose terminals of the plane coil and electrode terminals of the semiconductor element to the second surface of the film. A wiring pattern consisting of conductive paste is filled in the through holes and extends therebetween along the second surface of the film so that the terminals of the plane coil are electrically connected to the electrode terminals of the semiconductor element by means of the wiring pattern.

Abstract: A high-insulated stud comprises a first columnar conductive terminal of a first height, a second columnar conductive terminal of a second height lower than the height of the first conductive terminal that is placed in a row with and at a distance from the first conductive terminal, an insulating pedestal, and a first groove open at the top and a second groove intersecting the first groove and shallower than the first groove at the top of the first conductive terminal and a third groove open at the top, which is parallel with the first groove and whose bottom face is almost the same height as the bottom face of the first groove, at the top of the second conductive terminal.

Abstract: A circuit sub-board for regulating constant power source and strengthening ground connections. The circuit sub-board is a double-layered printed circuit board having a large surface power-source layer and a ground-connection layer. The circuit sub-board is utilized to cover the insufficiently ground-covered main board signaling lines as well as insufficiently ground-connected power and ground signaling lines on the main board. With the installation of the circuit sub-board, signals can be transmitted more reliably and with less interference.

Abstract: A wiring board and electrode of a semiconductor element are connected with each other by the method of wire bonding, and problems arising from the thermal stress generated in the process of mounting are overcome. There is provided a wiring board comprising: a first face joined to an electrode forming face of a semiconductor element 10; and a second face on the opposite side of the first face, a wiring pattern 16 being formed on the second face, a land 24 joined to an external connecting terminal 22 being formed at one end of the wiring pattern, a wire bonding section 16a connected with a bonding wire 40 being formed at the other end of the wiring pattern, wherein the land 24 is supported by a buffer layer 34 for reducing the thermal stress generated when the semiconductor element, to which the wiring board is attached, is mounted via the external connecting terminals, and the wire bonding section 16a is supported by a bonding support layer 36 having an elastic modulus capable of allowing wire bonding.

Abstract: A method for forming connections within a multi-layer electronic circuit board 10. In one non-limiting embodiment, the method includes selectively forming air bridges over portions of the circuit board 10 and selectively collapsing the air bridges with a metallurgical bonding tool, effective to interconnect layers of the circuit board 10.

Abstract: A substrate for mounting an optical component includes a first groove formed in a surface of a substrate, a second groove formed in the surface of the substrate, the second groove having a depth greater than the first groove. In the present invention, the first groove and the second groove are related to each other by the following equation, (2D sin &thgr;)/R≧C where D denotes a depth of the first groove, &thgr; denotes an angle between a horizontal plane and a slanted surface of the first groove (0°<&thgr;<90°), R=F/E (E denotes an etching rate of a slanted surface of the first groove, F denotes an etching rate of a bottom surface of the groove, C denotes a top opening width of the groove.

Abstract: A printed circuit board with a reinforcing pattern. The printed circuit board includes lands formed in a wiring pattern at positions corresponding to formation positions of external connection electrode terminals, a pattern protective film having openings which are opened at the formation positions of the lands; wherein the diameter of each of the openings of the pattern protective film is set to be larger than the outside diameter of each of the lands, and a reinforcing pattern extends outwardly from the outer peripheral edge of each of the lands and the extension end of the reinforcing pattern is covered with the pattern protective film, thereby preventing occurrence of cracks in solder balls formed on the lands and enhancing the shear strength of the solder balls.

Abstract: An apparatus for mounting an electronic device on a substrate without soldering is disclosed. The apparatus includes a body and a plurality of cantilever beams extending from the body. The apparatus is mounted on the substrate. The electronic device is placed within the apparatus. In one embodiment, the cantilever beams press against the electronic device. In another embodiment, the cantilever beams engage the substrate. The apparatus presses an array of electrical contacts of the electronic device (e.g., interconnection balls) against corresponding metal pads of the substrate, thereby forming an electrical connection.

Abstract: A plain layer in a forming area of a measuring wiring pattern is patterned so that its copper-containing amount may be coincided with a copper-containing amount in a forming area of a measurement target signal wiring pattern. Thereby, it is possible to coincide a thickness of an insulating layer in the forming area of the measuring wiring pattern with a thickness of the insulating layer in the forming area of the measurement target signal wiring pattern, thus reducing a measuring error of the characteristic impedance based on a difference of a thickness of the insulating layer. Using the measuring wiring pattern, it is possible to measure a correct characteristic impedance of the measurement target signal wiring pattern.

Abstract: A circuit board including differential bus traces on or buried within both sides of the board, interconnecting electronic devices such as disk drives, processors, and connectors for external cables. Via fields, which mimic the size and configuration of the device and cable connector fields, are located between each connector on the board. The via fields link bus traces on or within one side of the board with respective bus traces on or within the other side of the board. The via fields may include subtle, unequal undulations in the trace patterns to provide equalization in the lengths of all trace pairs. The via fields and the connector fields both include repetitive conductor order reversals in the trace connections on opposing sides of the board, to reduce crosstalk between channels. The via fields may be oriented parallel with respect to collinearly arranged devices, or orthogonal with respect to devices or connectors which are parallel.

Abstract: A power source (ground) line, which would have been formed with a broad conducting path is divided into multiple fine-line interconnections. A short-circuiting joint is formed to connect between the divided, multiple fine-line interconnections.

Abstract: A multi-layer circuit board includes first, second, third, fourth, fifth, sixth and seventh insulating substrates; first, second, third, fourth and fifth signal wiring layers; first and second ground wiring layers; and a power wiring layer. Each of the first and seventh insulating substrates has a thickness ranging from 2.5 to 6.5 mil. Each of the second, fourth and sixth insulating substrates has a thickness ranging from 3 to 9 mil. Each of the third and fifth insulating substrates has a thickness ranging from 3 to 23 mil. The first signal wiring layer has a first resistance with respect to the first ground wiring layer. The second signal wiring layer has a second resistance with respect to the first ground wiring layer and the power wiring layer. The third signal wiring layer has a third resistance with respect to the first ground wiring layer and the power wiring layer. The fourth signal wiring layer has a fourth resistance with respect to the second ground wiring layer and the power wiring layer.

Abstract: A double-sided circuit card assembly comprises first and second printed wiring boards having first and second sets of electrical contacts mounted thereon, and a signal cross-over interconnect member interposed between the first and second printed wiring boards and bonded thereto so as to form therewith a three-component laminate. The cross-over interconnect member comprises a metal frame member having a slot defined therethrough, and a flex circuit member, having a third set of electrical contacts mounted thereon, is passed through the slot and bent around an internal edge portion of the frame member so as to electrically interconnect the first and second sets of electrical contacts of the first and second printed wiring boards. In this manner, the number of interconnection sites is enhanced, the fabrication of the electrical connections is facilitated, and the flex circuit member is disposed internally of the laminate structure so as not to be exposed to external environmental factors.

Abstract: A printed circuit board includes a first helical conductive trace and a second helical conductive trace. The first helical conductive trace extends generally along a longitudinal axis of a layer of the printed circuit board. The first helical conductive trace is provided successively: along a first surface, from the first surface through the layer to a second surface, along the second surface, and from the second surface through the layer to the first surface. The second helical conductive trace extends generally along the longitudinal axis of the layer of the printed circuit board. The second helical conductive trace is provided successively: along the second surface, from the second surface through the layer to the first surface, along the first surface, and from the first surface through the layer to the second surface. A method is also provided.