Abstract: Each wiring layer of a multilayered wiring substrate includes signal wirings disposed in parallel with one another, and dummy wirings disposed at each side parallel to the signal wirings of the signal wiring group made by signal wiring, respectively. The dummy wirings have the same shape as the signal wirings, and are disposed in parallel to the signal wirings at the same intervals as that in the signal wirings. Through holes are formed in the respective clearances among the signal wirings. Dummy through holes having the same shape as the through holes are formed between the dummy wiring and signal wiring. A conductive layer is formed on the inner wall of the through holes. The multilayered wiring substrate is able to reduce or eliminate the delay time difference between signals that propagate along the signal wirings.

Abstract: A multi-layer solid structure and method for forming a thermal interface between a microelectronic component package and a heat sink so that the structure has a total thermal resistance of no greater than about 0.03° C.-in2/W at a pressure of less than 100 psi. The structure comprises at least two metallic layers each of high thermal conductivity with one of the two layers having phase change properties for establishing low thermal resistance at the interface junction between the microelectronic component package and the heat sink.

Abstract: A method, apparatus, and article of manufacture for providing power from a first circuit board having a first circuit board first conductive surface and a first circuit board second conductive surface to a second circuit board having a second circuit board first conductive surface and a second circuit board second conductive surface is described. The apparatus comprises a first conductive member, including a first end having a first conductive member surface electrically coupleable to the first circuit board first conductive surface and a second end distal from the first end having a first conductive member second surface electrically coupleable to the second circuit board first surface.

Abstract: A printed circuit board includes an insulative substrate. A first conductive layer having a predetermined width and length is formed on the insulative substrate, the first conductive layer extending in a first direction. A first insulative layer is formed over the first conductive layer. A circuit pattern having a narrower width than that of the first conductive layer is provided in parallel with the first direction of the first conductive layer, the circuit pattern being formed on the first insulative layer. A second insulative layer is formed over the circuit pattern. A pair of grooves is formed alongside the entire length of both sides of the circuit pattern and in the first and second insulative layers so as to expose the first conductive layer, the pair of grooves extending in a second direction parallel to the first direction so as to sandwich the circuit pattern there between.

Abstract: An improved method for making prototypes as well as finalized circuit boards consisting of terminal pads affixed to a circuit board with raised circuit trace interconnects between the terminal pads. The raised interconnects between the terminal pads are selectively cut and removed to form the remaining circuit board traces.

Abstract: A PCSB assembly including a PCSB; a first plurality of LVD SCSI bus signal trace pairs formed in the PCSB; a second plurality of LVD SCSI bus signal trace pairs formed in the PCSB and positioned next adjacent one another for the entire length thereof comprising a RESET signal trace pair, a SELECT signal trace pair and a BUSY signal trace pair.

Abstract: AC-ground plane is for a semiconductor chip adapted to be mounted on a supporting member in a chip package, wherein said ground plane comprises at least one first capacitor plate provided within said chip, and at least one second capacitor plate provided on said supporting member, said first and second capacitor plate being separated by a dielectric layer and capacitively coupled to each other via this layer, and said ground plane comprising at least one first conducting member, said first conducting member being at least one electrically conducting via extending through said supporting member and electrically coupled in series with said second capacitor plate.

Abstract: A technique for electrically interconnecting a signal between a first circuit board and a second circuit board is disclosed. In each board, at least one signal conductor is shielded by an electrically conductive shield. Multiple conductors may be shielded by the same shield. A first opening is formed in the electrically conductive shield of the first circuit board and a second opening is formed in the electrically conductive shield of the second circuit board so as to expose the signal conductor in the each circuit board. An electrically conductive adhesive, reflowed solder paste, or interposer/elastomer device is applied surrounding at least one of the openings and may further be applied within at least one of the openings. The first circuit board and the second circuit board are then positioned such that the first opening and the second opening are aligned and a signal propagating along the first signal conductor is electrically interconnected to the second signal conductor.

Abstract: An opening is formed in resin by a laser beam so that a via hole is formed. Copper foil, the thickness of which is reduced to 3 &mgr;m by etching to lower the thermal conductivity, is used as a conformal mask. Therefore, an opening is formed in the resin and the number of irradiation of pulse-shape laser beam is reduced. Thus, occurence of undercut of the resin, which forms an interlayer insulating resin layer, can be prevented and the reliability of the connection of the via holes can be improved.

Abstract: In the production of a printed wiring board comprising innerlayer conductor circuits 161, 131 arranged among insulating layers 101˜103 and blind via-holes 141, 142 formed from an outermost surface of the insulating layer toward the innerlayer conductor circuit, an opening hole 160 is previously formed in a central portion of the innerlayer conductor circuit 161 located at the bottom of the blind via-hole 141, and laser beams are irradiated from the outermost surface of the insulating layer to form the blind via-holes 141, 142. Thereafter, a metal plated film is formed on surfaces of the innerlayer conductor circuits 13, 161 and the blind via-holes 141, 142.

Abstract: A method of fabricating a printed circuit device including an electrically insulating substrate, and first, second, and third sets of conductors formed on a top surface of the substrate is disclosed. The method includes forming an oxide layer on the set of second conductors; forming a solder mask on the oxide layer; forming a composite layer on the first set of conductors; and forming a solder layer on at least a portion of the third set of conductors.

Abstract: An electronic assembly includes one or more conductive clamps (302, 304, FIG. 3), which are used to supply current to an integrated circuit (IC) package (308). The conductive clamps are attached to a printed circuit (PC) board (312), which supplies the current to the IC package over one clamp, and receives returned current from the IC package over another clamp. Each clamp contacts a contact pad (330) on the surface of the PC board, and contacts another contact pad (334) on the top surface of the IC package. Vias (338, 339) and conductive planes (340, 342) within the package then carry current to and from an IC (e.g., IC 306) connected to the package. In another embodiment, the clamp (904, FIG. 9) holds a conductive structure (902) in place between the PC board contact pad (908) and the IC package contact pad (914), and current is carried primarily over the conductive structure, rather than over the clamp.

Abstract: The present invention pertains to a multilayer flexible wiring board. The multilayer flexible wiring board including first and second patterned wiring layers, a resin film interposed between a surface of the first wiring layer and a surface of the second wiring layer, and a bump connected to the surface of the second wiring layer, wherein the resin film is adapted to form an opening when the bump to force into the resin film and an ultrasonic wave is applied to the bump and the bump is left in the opening to electrically connect the top of the bump to the first wiring layer.

Abstract: A low-profile multi-chip module is provided, wherein two or more chips are integrated in a package unit connected to a printed circuit board (PCB), to provide a manifold level of functionality and data storage capacity. The multi-chip module includes at least a first chip and a second chip connected to a predetermined position on an active surface of the first chip by chip-on-chip technology, allowing the active surface of the first chip to be further mounted to a substrate by flip-chip technology. The substrate is attached to the PCB by surface-mount technology, and interposed between the first chip and the PCB. At least a passive component is mounted on the PCB at a position beside the substrate and underneath the second chip. This structure allows the use of a PCB having a smaller layout area for implementing the multi-chip module, thereby desirably reducing the overall structural profile.

Abstract: In a multilayer printed circuit board having a conductor pattern, covered with an insulation layer having via holes, these via holes are filled with a conductor by means of electroless nickel plating or electroless copper plating.

Abstract: A solder connecter assembly having a printed wiring board, an electrode formed on the printed wiring board, a semiconductor package, a pad formed on the semiconductor package, a resist formed on the printed wiring board and having an opening of the resist around the electrode, a solder ball disposed between the electrode and the pad, and a resin fillet formed in the opening and in a vicinity of a connecting part between the solder ball and the electrode.

Abstract: A virtual mirror “crossover” package includes two groups of electrically interconnected pairs of first and second connection points. Within each group, the set of first and second connection points are positioned adjacent opposing edges of a chip carrier or other package, such that one group of connection point pairs can be connected to a first bus running in an “X” direction on a substrate, while the other group of connection point pairs can be connected to a second bus running in a “Y” direction perpendicular to the “X” direction. The virtual mirror crossover package can be used in an array of packages in which the packages in each column are connected to a unique system bus, and a row of packages containing a virtual mirror crossover package is also connected to an inter-system bus (such as a cluster bus) for providing communication between the various system buses via the inter-system bus.

Abstract: A pin standing resin substrate 311 comprises a resin substrate 313 and many pins 301 soldered (HD) to a pin-pad 317A, the resin substrate comprising such as a resin and having a pin-pad 317AP whose diameter of a portion exposed in a main surface 313A is 0.9 to 1.1 mm. The kovar-made pin 301 is previously heat-treated at 700° C., whereby Vickers hardness is made Hv=around 150, and the pin has a rod-like portion 301A of a diameter being 0.3 mm and an enlarged diameter portion 301B shaped in disk being 0.60 to 0.70 mm and thickness being 0.15 to 0.20 mm, the enlarged diameter portion being formed at one end of the rod-like portion 301A. This enlarged diameter portion 301B is soldered to the pin-pad.

Abstract: The present invention provides a unique, high density, electronic package having a conductive composition for filling vias or through holes to make reliable vertical or Z-connects from a dielectric layer to adjacent electrical circuits. The through holes may be plated or non-plated prior to filling. A description for making high density electronic packaging using this feature is also disclosed.

Abstract: A multi-layer printed circuit board includes a core layer having a first circuit patterns formed on the upper and lower surface of a first insulation layer and via-holes in which a conductive layer is formed to electrically connect with the first circuit patterns. Built-up layers are formed on the upper and lower side of the core layer and have second circuit patterns electrically connected with the first circuit pattern by means of a via-holes in which conductive layers are formed to electrically connect the first circuit patterns of the core layer and the second circuit patterns of the upper and/or lower built-up layers. The via-holes in the core layer and the via-holes in the built-up layers are formed from an each side/both sides of the core layer and from the built-up layers toward the core layer, whereby interconnection of the circuit patterns is obtained without using through-holes and permitting shortening of the wiring and higher integration.